Video ADC Phase Alignment Using Multi-Phase Ringing Detection
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Solution Overview
Problem
Existing video display systems face challenges in accurately sampling analog video signals due to ringing during pixel transitions, leading to poor fidelity and high memory requirements, especially at high pixel rates and resolutions, and conventional phase optimization methods degrade the image or require excessive memory.
Innovation Solution
A method and circuitry that optimize the sample phase by comparing pixel values at different phases within a pixel period, using counters to determine the optimal sampling point without disturbing the data path, and measuring drift in sample frequency, allowing for efficient sampling across various resolutions and frame rates without degrading the image.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the pixel rate is increased to support high resolution displays, then the switching speed of the analog video signal is improved, but the ringing amplitude increases and the sampling accuracy deteriorates
Solution Approach 1:
The system performs preliminary actions by sampling the analog video signal at multiple different phases within the pixel period before determining the optimal sampling point. This allows the system to anticipate and avoid ringing periods by pre-evaluating multiple sampling opportunities, thereby maintaining sampling accuracy even at high pixel rates where ringing amplitude is increased.
Solution Approach 2:
The system dynamically adjusts the sampling phase based on real-time analysis of the analog video signal characteristics. By making the sampling phase variable rather than fixed, the system can adapt to changing signal conditions and select the optimal moment within each pixel period to avoid ringing, thus maintaining measurement precision while supporting high switching speeds.
2Measurement precision
If the sampling point is varied to avoid ringing, then the sampling accuracy is improved, but the memory requirements and sample rate increase
Solution Approach 1:
The system segments the pixel period into multiple sampling phases and evaluates them independently. By dividing the sampling process into discrete phases that can be processed separately, the system can identify the optimal sampling point without requiring storage of all possible sampling results, thereby reducing memory requirements while maintaining sampling accuracy.
Solution Approach 2:
The system creates a simplified representation or copy of the sampling process that allows evaluation of multiple phases without requiring full storage of all sampling data. This copying approach enables the system to analyze and compare different sampling phases mentally or through lightweight processing, eliminating the need for large memory resources while still achieving accurate sampling point selection.
3Manufacturing precision
If the sampling phase is optimized for a specific resolution, then the image fidelity is improved, but the system's adaptability to different resolutions decreases
Solution Approach 1:
The system implements a universal sampling optimization method that can adapt to multiple resolutions and frame rates through a single unified approach. By establishing a general framework for phase optimization that works across different display parameters, the system achieves multi-functionality, allowing it to maintain image fidelity across various resolutions without requiring resolution-specific optimization procedures.
Solution Approach 2:
The system utilizes parameter changes by adjusting the sampling phase based on the detected pixel rate and signal characteristics rather than being fixed for a specific resolution. This parameter-adjustable approach allows the same optimization mechanism to adapt to different resolutions and frame rates, maintaining image fidelity across diverse display configurations without sacrificing versatility.
Data Source
AI summary
A digital video system (2) is disclosed, in which an analog input video signal is sampled at an optimum sample phase (Pnc), and converted to a digital datastream for display. A phase-locked loop (12) generates a plurality of sample clock phases. One of the sample clock phases (Pnc) is applied to an analog-to-digital converter (10), which digitizes the analog input video signal accordingly. Phase alignment circuitry (20) is provided that includes three sample-and-hold circuits (22b, 22c, 22a) that sample the analog input video signal, in parallel with the analog-to-digital converter (10), at times before, at, and after the current sample clock phase used by the analog-to-digital converter (10). The earlier and later sampled voltages are compared against the current sampled voltages to generate difference voltages that are each compared against a threshold voltage (Vthr). The numbers of times that the difference voltages exceed the threshold voltage over a field or frame is analyzed according to various techniques, to determine whether and in which direction to adjust the position of the current sample clock phase within the pixel period.