Video Packet Bit Rate Adjustment via Integer Decimal Tick Separation
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Solution Overview
Problem
Conventional methods for adjusting the output bit rate of video packets in MPEG-2 Transport Streams require external hardware and separate clocks, leading to inefficiency and potential data loss due to complex circuitry and the need for initializing the output interface.
Innovation Solution
A method and apparatus that separate the counting value of packet output time into integer and decimal parts using programmable registers and counters, allowing precise bit rate adjustment without external hardware, by generating output signals based on tick increments and managing carry overs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external variable clock sources and separate hardware circuits are used to adjust bit rate, then bit rate adjustment capability is improved, but device complexity and circuit complexity increase
Solution Approach 1:
The patent replaces external hardware clock sources and separate circuitry with a software-based bit rate adjustment mechanism. The processor controls the output interface clock using programmable counters and tick values, eliminating the need for external variable clock sources and separate DDS chips, thereby reducing device complexity while maintaining bit rate adaptability
Solution Approach 2:
The patent makes the existing output interface clock serve multiple functions: it is used both for operating the MPEG-2 TS packet processing logic and for generating the output interface clock signal. By making the clock universal and controllable via software parameters, the system achieves bit rate adjustment capability without adding dedicated hardware for each function
2Measurement precision
If external hardware and separate clocks are installed for bit rate adjustment, then bit rate control precision is improved, but ease of manufacture and installation deteriorate
Solution Approach 1:
The patent replaces physical hardware modifications with software-based control. Bit rate precision is achieved through programmable tick values and counter mechanisms that can be configured via software, eliminating the need for separate hardware installation and making the system easier to manufacture and install while maintaining precise control
Solution Approach 2:
The patent achieves precise bit rate control by changing software parameters (tick values, counter initial values) rather than modifying hardware. This allows flexible and precise bit rate adjustment without additional manufacturing steps or hardware installation, improving ease of manufacture while maintaining control precision
3Adaptability or versatility
If output interface is initialized to change clock during operation, then adaptability is improved, but data loss occurs and reliability deteriorates
Solution Approach 1:
The patent performs preliminary configuration of bit rate parameters (tick values, counter settings) before operation begins. This allows the system to change bit rates dynamically during operation without initializing the output interface, as all necessary parameters are pre-configured and can be adjusted through software without causing data loss
Solution Approach 2:
The patent replaces the hardware initialization process with software-based parameter adjustment. By using programmable counters and tick values controlled through software, the system can dynamically change clock rates without the need to initialize the output interface, thereby preventing data loss and improving reliability while maintaining adaptability
Data Source
AI summary
An apparatus for adjusting an output bit rate of a TS packet includes: a TS processing unit for processing the TS packet; an output buffer for buffering and outputting TS packets processed by the TS processing unit; and a bit rate adjustment unit for separating a counting value of packet output time into an integral part and a decimal part by a preset reference cipher according to ticks, generating TS packet output signals for outputting one TS packet stored in the output buffer if a value obtained by performing first counting according to the ticks reaches a value of the integral part, resetting a first count value, and decreasing the first count value by one if a carry occurs in a value obtained by performing second counting for achieving an increment by the value of the stored decimal part whenever the TS packet output signals are generated.