Video Processing Circuit Buffering for Bubble Cycle Reduction

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Solution Overview

Problem

Conventional video processing circuits face significant performance drops due to bubble cycles caused by switching between stages and block size changes during size-based parallel computations, particularly in video coding standards like VVC.

Innovation Solution

A video processing circuit with a high-performance serial architecture that includes a first buffer and computation circuit to generate and store processing results for consecutive blocks, using a ring FIFO TM buffer to buffer 1st stage results and a stage decision-making switch to adaptively switch between stages, and SIVO and VISO buffers to manage data throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a single transform kernel is reused for both 1st stage and 2nd stage processing, then computation resource is saved, but bubble cycles occur due to switching between stages and block sizes

Engineering Contradiction:

Improvecomputation resourceVSAvoidbubble cycles

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The processing architecture is segmented into dedicated 1st stage processing units and 2nd stage processing units that operate independently and in parallel. This segmentation eliminates the need for switching between different processing modes, thereby removing bubble cycles while maintaining computational efficiency through parallel operation of specialized units.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The 1st stage processing is performed in advance on all blocks before 2nd stage processing begins. By completing the 1st stage transformation and buffering results beforehand, the system prepares data for 2nd stage processing without interruption, eliminating waiting periods and bubble cycles that would occur with sequential processing.

Inventive Principle:

Principle #10Preliminary action

2Device complexity

If conventional sequential processing is used to handle blocks of different sizes, then device complexity is reduced, but productivity drops due to frequent stage switching

Engineering Contradiction:

Improveprocessing architectureVSAvoidprocessing throughput

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The system dynamically processes multiple block sizes simultaneously using dedicated processing units configured for specific block dimensions. Each processing unit is optimized for particular block sizes (e.g., 4x4, 8x8, 16x16), allowing the system to adapt to varying block size requirements without reconfiguration overhead or stage switching, thereby maintaining high productivity across different video content types.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

Multiple processing streams for different block sizes are merged into a unified parallel processing architecture where 1st stage and 2nd stage units work concurrently. This combining of processing paths eliminates the need for sequential stage switching while handling variable block sizes, improving throughput without significantly increasing overall system complexity through shared buffering and control mechanisms.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12563212B2Video processing circuit for performing size-based parallel in parallel out computation with bubble cycle reduction

Publication Date: 2026.02.24 MEDIATEK INC

AI summary

A video processing circuit includes a first buffer and a computation circuit. Before a second one-dimensional processing operation is performed upon a plurality of consecutive blocks in a second direction, the first computation circuit generates a first processing result for each of the plurality of consecutive blocks by performing a first one-dimensional processing operation upon each of the plurality of consecutive blocks in a first direction that is different from the second direction, and further stores a plurality of first processing results of the plurality of consecutive blocks into the first buffer.