Integrated Video Clock Generator for Multi-Format Low-Jitter Sync
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Solution Overview
Problem
Current video image systems face challenges in processing multiple video formats efficiently due to the need for separate components to generate clock signals, leading to increased complexity and potential for high clock jitter.
Innovation Solution
An integrated video clock signal generator using a master phase-locked loop (PLL) with an off-chip voltage-controlled oscillator (VCO) produces synchronized on-chip oscillator signals, which drive slave PLL circuits to generate pixel clock signals aligned with horizontal and vertical synchronization signals, reducing jitter and enabling support for multiple formats within a single chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate components are used to generate clock signals for different video formats, then each format can be supported with dedicated hardware, but device complexity increases and more components are required
Solution Approach 1:
The patent implements a universal clock generator architecture where a single master PLL with programmable dividers and a single on-chip VCO can generate clock signals for multiple video formats (SD, HD, and various frame rates). This multi-functional design eliminates the need for separate discrete PLLs for each format, reducing component count while maintaining format versatility through software-controlled programming of division ratios and timing parameters.
2Adaptability or versatility
If multiple discrete PLLs are used to support different video formats, then each format receives dedicated clock generation, but the number of components and potential for clock jitter increases
Solution Approach 1:
The patent merges multiple discrete PLL functions into a single integrated PLL circuit with a shared VCO. This consolidation ensures that all video formats are derived from the same stable frequency reference and phase-locked loop, eliminating jitter introduced by multiple independent oscillators and PLLs. The unified architecture maintains format-specific timing requirements while ensuring consistent clock quality across all outputs.
3Device complexity
If a single-chip solution is implemented, then device complexity and component count are reduced, but integration of multiple video format support becomes more difficult
Solution Approach 1:
The patent employs dynamic, programmable division ratios and timing parameters within the integrated PLL that can be configured via control signals to match different video format requirements. The on-chip VCO frequency and divider ratios are dynamically adjusted based on the selected format (SD, HD, frame rates), allowing a single static chip to provide dynamic adaptation to multiple formats without requiring separate hardware for each configuration.
Data Source
AI summary
An integrated video clock signal generator in which a master phase-locked loop (PLL) control circuit uses an off-chip voltage-controlled oscillator (VCO) to produce an on-chip oscillator signal in synchronization with a horizontal reference signal related to a horizontal video synchronization signal. This on-chip oscillator signal drives one or more slave PLL circuits which provide respective one or more on-chip PLL signals synchronized with the on-chip oscillator signal. In accordance with a preferred embodiment, each on-chip PLL signal is a pixel clock signal with a plurality of clock signal pulses which is synchronized with a vertical reference signal related to a vertical video synchronization signal.