Wireless Video Receiver Clock Recovery Using Start-of-Frame Sync
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Solution Overview
Problem
In wireless video transmission systems, especially for high-definition video, the bandwidth required for transmitting synchronization signals reduces the available bandwidth for video data, and existing solutions are inadequate for generating a synchronized clock without frame buffering, leading to video source jitter and alignment issues.
Innovation Solution
An apparatus that extracts the start of frame (SOF) indication using a symbol detection and synchronization module to generate a pixel-rate clock, allowing real-time adjustment of the video clock using a phase-locked loop (PLL) without transmitting horizontal and vertical synchronization signals, thereby conserving bandwidth and accommodating jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If horizontal and vertical synchronization signals are transmitted over the wireless link, then video frame synchronization is achieved, but available bandwidth for video data transmission is reduced
Solution Approach 1:
The patent extracts only the essential synchronization information (start of frame indication) from the complete horizontal and vertical synchronization signals. This extracted minimal information is sufficient to generate the pixel-rate clock at the receiver without transmitting the full synchronization signal set, thereby resolving the bandwidth-synchronization contradiction.
Solution Approach 2:
The patent introduces an intermediary approach where the receiver generates the pixel-rate clock locally using a phase-locked loop (PLL) that is controlled by the extracted start of frame indication. This intermediary clock generation mechanism eliminates the need to transmit detailed synchronization signals while maintaining accurate video frame synchronization.
2Quantity of substance
If a local oscillator is used to generate the video clock, then bandwidth is conserved, but clock synchronization with the video source becomes difficult without frame buffering
Solution Approach 1:
The patent implements a feedback mechanism through the phase-locked loop (PLL) that continuously adjusts the locally generated pixel-rate clock based on the extracted start of frame indication from the received video signal. This feedback ensures that the local clock remains synchronized with the video source without requiring frame buffering, resolving the contradiction between bandwidth conservation and clock synchronization reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate pixel-rate clock generation for reconstructing video frames, ensuring synchronization without frame buffering, and maintaining bandwidth for high-definition video transmission, applicable to systems with minimal or no buffering.
Implementation Method 1
The invention uses signaling through the wireless link and reports to the receiver when Hsync occurs in the video source. The receiver then generates the video clock from the received signal using, for example, a phase-locked loop (PLL).
Data Source
AI summary
An apparatus for receiving essentially uncompressed HDTV video must generate an accurate pixel-rate clock to enable the reconstruction of a video frame. The clock pixel-rate generated must match a received video pixel-rate. In such system, signals for generation of horizontal and vertical synchronization are not transmitted over the wireless link to conserve the use of bandwidth. In the invention, a start of frame (SOF) indication is extracted by a symbol detection and synchronization (SDS) module and is used to generate the pixel-rate clock.