Video Read Clock Synchronization to Reduce Frame Memory Delay
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Solution Overview
Problem
Existing image processing devices experience significant time lag in outputting video signals due to the frame memory becoming empty when read speed exceeds write speed, resulting in delayed image display.
Innovation Solution
An image processing device that utilizes a memory, horizontal synchronization detection circuit, phase comparator, lock circuit, PLL, and frequency divider to synchronize the read clock signal with the horizontal synchronization signal, allowing the video signal to be read at the correct timing, thereby reducing the delay period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the read speed from the frame memory is faster than the write speed, then the video signal can be read in advance, but the frame memory may become empty causing a delay of one or two frames
Solution Approach 1:
The patent implements a feedback mechanism by detecting the horizontal synchronization signal from the input video signal and using a phase comparator to compare its phase with the read clock signal. The lock circuit adjusts the read clock signal phase based on this comparison, creating a closed-loop feedback system that dynamically synchronizes reading operations with the actual video signal timing, thereby preventing buffer underflow while minimizing delay.
Solution Approach 2:
The system uses the horizontal synchronization signal inherently present in the input video signal itself to control the reading timing, rather than relying on external clock signals. This self-service approach allows the system to automatically adapt to the input signal's timing characteristics, ensuring synchronized reading without requiring separate timing reference sources.
2Reliability
If reading is performed after input video signals are written for one or two frames, then the frame memory has sufficient data, but the time lag of image display relative to the input video signals is large
Solution Approach 1:
The phase comparator continuously monitors the phase relationship between the horizontal synchronization signal and the read clock signal, providing real-time feedback to the lock circuit. This enables dynamic adjustment of the read timing to match the actual video signal timing, allowing the system to read data with minimal delay while ensuring data availability through continuous synchronization.
Solution Approach 2:
The system transitions from a static, fixed-delay reading approach to a dynamic, adaptive reading mechanism. The read clock signal's phase is continuously adjusted based on the detected horizontal synchronization signal, allowing the system to adapt its reading timing in real-time to minimize delay while maintaining data availability.
3Ease of operation
If the read clock signal is not synchronized with the horizontal synchronization signal, then the reading operation is simple, but the output video signal timing does not match the input video signal timing
Solution Approach 1:
The phase comparator provides continuous feedback on the phase difference between the read clock signal and the horizontal synchronization signal. This feedback enables the lock circuit to automatically adjust the read clock signal timing, maintaining precise synchronization without requiring complex manual timing adjustments or overly complicated reading operations.
Solution Approach 2:
The horizontal synchronization signal acts as an intermediary reference that mediates between the simple read clock signal and the timing requirements of the input video signal. By using this intermediate synchronization signal, the system achieves accurate timing alignment while keeping the reading operation relatively simple.
Data Source
AI summary
The disclosure includes a memory, a horizontal synchronization detection circuit, a phase comparator, a lock circuit, a PLL, and a frequency divider. The memory that reads out a written video signal in response to a read clock signal and outputs it as an output video signal. The horizontal synchronization detection circuit detects a horizontal synchronization signal from the video signal. The phase comparator generates a phase difference signal indicating a phase difference between the horizontal synchronization signal and a frequency-divided clock signal. The lock circuit receives a free-running clock signal and generates a reference clock signal in which a phase signal is shifted by an amount of the phase difference indicated by the phase difference signal. The PLL generates the read clock signal that is locked to the phase of the reference clock signal. The frequency divider generates the frequency-divided clock signal by dividing the read clock signal.