Video Data Regrouping for Byte-Aligned Host Memory

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Solution Overview

Problem

High-speed video streaming protocols typically transmit interleaved luminance and chrominance data, which requires host computers to separate and rebuffer the data, limiting processing rate and bandwidth due to non-byte-aligned pixel components.

Innovation Solution

A peripheral device, such as a network interface controller or computational accelerator, offloads parsing and buffering by separating luminance and chrominance data and justifying pixel components to be byte-aligned in memory, reducing the processing burden on the host computer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If interleaved luminance and chrominance data are transmitted according to high-speed video streaming protocols, then video data transmission is achieved, but the host computer's processing rate and bandwidth are limited due to the need to separate and rebuffer the data

Engineering Contradiction:
Improvevideo data processing rateVSAvoiddata separation and rebuffering complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The peripheral device performs preliminary separation of luminance and chrominance data during the reception phase, before the host computer needs to process the video data. This advance preparation eliminates the need for the host computer to perform time-consuming separation and rebuffering operations, thereby improving processing rate without increasing host computer complexity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The peripheral device acts as an intermediary between the network interface and the host computer, handling the complex tasks of data separation and rebuffering. This intermediary function protects the host computer from complexity while maintaining high video data processing throughput

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If pixel components are stored in non-byte-aligned format in memory, then interleaved video data structure is maintained, but processing efficiency is reduced due to misalignment

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidbyte-alignment precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The peripheral device changes the storage parameter of pixel components from non-byte-aligned to byte-aligned format in memory. This parameter transformation improves processing efficiency by enabling optimized memory access patterns and CPU operations, while the peripheral device handles the conversion overhead without impacting host computer performance

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11700414B2Regrouping of video data in host memory
Publication Date: 2023.07.11 MELLANOX TECHNOLOGIES LTD(IL)
  • US11700414B2 patent drawing
  • US11700414B2 patent drawing
  • US11700414B2 patent drawing

AI summary

Apparatus for data communications includes a host interface, which is configured to be connected to a bus of a host computer having a processor and a memory. Processing circuitry, which is coupled to the host interface, is configured to receive video data with respect to a sequence of pixels, the video data including data words of more than eight bits per pixel for at least one pixel component of the pixels, and to write the video data, via the host interface, to at least one buffer in the memory while justifying the video data in the memory so that the successive pixels in the sequence are byte-aligned in the at least one buffer.