Video Data Packing for Bus Bandwidth Utilization
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Solution Overview
Problem
Conventional systems for transmitting video data over a data bus are inefficient due to the presence of unused bits, which occupy bandwidth and reduce bus availability for other users.
Innovation Solution
Implementing a packing technique that rearranges video data to fill unused spaces within data words, allowing for transmission in fewer clock cycles and increasing bus availability by using a memory controller to pack data and a video display controller to unpack it back to its original format.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If video data is transmitted in conventional format with unused bits, then the data structure is simple, but the bus bandwidth utilization is low and transmission efficiency is reduced
Solution Approach 1:
The memory controller performs preliminary packing of video data before transmission onto the bus. By pre-arranging the data in packed format in memory, the system eliminates the need for complex real-time packing operations during transmission, thereby improving bus bandwidth utilization while managing complexity through dedicated preprocessing hardware
Solution Approach 2:
The patent introduces an intermediary packing/unpacking mechanism between the memory controller and video display controller. The memory controller packs data before bus transmission, and the video display controller unpacks it after reception. This intermediary process optimizes bus utilization while maintaining compatibility with standard video data formats at the interfaces
2Loss of time
If unused bits are transmitted along with video data, then the data alignment is simple, but the transmission time increases and bus availability for other users decreases
Solution Approach 1:
The system performs preliminary packing of video data in the memory controller before transmission. By pre-organizing multiple pixels into compact data words that eliminate unused bits, the system reduces transmission time while the hardware automatically handles the alignment complexity through dedicated packing logic
Solution Approach 2:
The patent changes the data representation parameters by transitioning from conventional formats with fixed unused bits to packed formats where data words contain only valid pixel information. This parameter change reduces the number of bits transmitted per pixel while hardware mechanisms maintain proper data alignment and ordering
3Speed
If video data is stored in conventional memory format, then the memory access is simple, but the number of clock cycles for transmission increases
Solution Approach 1:
The memory controller performs preliminary packing of video data from conventional memory format into compact transmission format before placing data on the bus. This pre-processing step increases transmission speed by reducing the number of clock cycles required, while the complexity is managed through dedicated hardware packing logic in the memory controller
Solution Approach 2:
The patent introduces packing and unpacking mechanisms as intermediaries between the simple memory access interface and the optimized transmission interface. The memory controller packs data for efficient bus transmission, and the video display controller unpacks it for display processing, thereby increasing speed while isolating complexity to dedicated hardware components
4Productivity
If more bits are transmitted per data word, then the data completeness is ensured, but the bus availability for other masters is reduced
Solution Approach 1:
The memory controller performs preliminary rearrangement and packing of video data before transmission. By pre-organizing data to eliminate unused bits and maximize information density per data word, the system increases bus availability for other masters while the hardware packing logic manages the rearrangement complexity
Solution Approach 2:
The patent changes the data organization parameters by transitioning from conventional formats with unused bits to packed formats where each data word contains maximum valid information. This parameter change increases bus availability by reducing transmission time, while dedicated hardware mechanisms handle the data rearrangement complexity
Data Source
AI summary
Systems and methods for rearranging valid data within a block of data for transmission along a data path are described herein. By utilizing previously unused bits in data words, the valid data can be transmitted in fewer clock cycles, thereby increasing the availability of the data bus to other masters. An exemplary embodiment of a system for transmitting data along a data bus includes one or more masters, one or more slaves, and a data bus interconnecting the masters and slaves. One of the slaves is a memory controller configured to access data from an external memory device. The memory controller may be further configured to pack video data for transmission along the data bus. One of the masters is a video display controller configured to feed video data to an external video display. The video display controller may be further configured to receive the packed video data and unpack the packed video data for transmission to the video display.