Motion Compensated Video Decoder Caching Method
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Solution Overview
Problem
Conventional video decoder systems face high power consumption and DRAM bandwidth issues due to large memory requirements for motion compensated video compression, especially in portable high-definition implementations, and traditional caching techniques are inefficient, leading to increased power usage and cache misses.
Innovation Solution
A caching method that fetches and stores only reference samples within a limited vertical range of the current target block, using a single valid bit per cache block, rather than address tags, to minimize cache misses and reduce DRAM bandwidth utilization, thereby reducing power consumption and overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional set associative caches are used with large cache blocks, then cache hit rate improves, but DRAM bandwidth utilization increases and power consumption increases due to transferring unused data
Solution Approach 1:
The patent segments the cache into multiple smaller ways (e.g., 4-way set associative instead of 8-way) and uses selective invalidation of cache ways based on motion vector analysis. This allows the system to maintain high cache hit rates by keeping relevant data while avoiding the power penalty of transferring and caching unnecessary data blocks.
Solution Approach 2:
The patent implements partial caching by invalidating specific cache ways that are not needed for the current motion compensation operation. Instead of caching all possible reference data, only the necessary portions are kept in cache, reducing DRAM bandwidth utilization and power consumption while maintaining adequate cache performance.
2Loss of energy
If traditional set associative caches are used with small cache blocks, then DRAM bandwidth utilization decreases, but cache miss rate increases and overhead from address tags increases
Solution Approach 1:
The patent dynamically adjusts the number of active cache ways based on the motion complexity and reference frame requirements. This dynamic configuration allows the system to optimize between cache hit rate and DRAM bandwidth utilization in real-time, adapting to different video sequences and motion patterns.
Solution Approach 2:
The patent changes the cache organization parameters by using fewer cache ways with selective invalidation rather than traditional many-way associativity. This parameter change reduces the overhead from address tags and improves cache efficiency while maintaining adequate hit rates through intelligent cache management.
3Device complexity
If cache block size is increased, then fewer cache blocks are needed, but address tag overhead increases and cache area increases
Solution Approach 1:
The patent segments the cache into multiple smaller ways, which reduces the address tag overhead per cache block. By using selective invalidation of these segmented ways, the system achieves efficient caching with reduced overhead compared to using fewer, larger cache blocks.
4Productivity
If DRAM access is increased to handle cache misses, then cache performance improves, but power consumption increases due to DRAM latency
Solution Approach 1:
The patent performs preliminary analysis of motion vectors to predict which cache ways will be needed before executing cache operations. This preliminary action allows the system to pre-validate cache ways and avoid unnecessary DRAM accesses, improving cache performance while reducing power consumption from DRAM latency.
Data Source
AI summary
A method for high performance caching is disclosed. The method generally includes steps (A) and (B). Step (A) may fetch a plurality of reference samples of a reference image from a first circuit to a cache of a second circuit. The cache may include a plurality of cache blocks and a plurality of valid bits. Each of the cache blocks generally corresponds to at most one of the valid bits. A size of the cache blocks may match a smallest read access size of the first circuit. Step (B) may transfer the reference samples having the corresponding valid bit set to valid from the cache to a processor of the second circuit.