Multi-Core Video Decoder Using Double Buffering for Parallel Slice Processing

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Solution Overview

Problem

Conventional video decoding methods using single-core processors are inefficient in utilizing the performance of multi-core processors, leading to complications in achieving parallel processing and resource utilization due to dependent data processing operations.

Innovation Solution

A multi-core processor-based video decoding method that interleaves calculations with data transfers, utilizing a first core to parse and allocate bitstreams into slices and a second core to decode and store macroblocks in auxiliary buffers, alternately transferring them to main memory while reconstructing images, allowing for simultaneous operations unaffected by motion compensation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data processing operations are made dependent on each other to ensure correct decoding, then decoding accuracy is improved, but parallel processing capability deteriorates

Engineering Contradiction:
Improvedecoding accuracyVSAvoidparallel processing capability
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides the video bitstream into multiple independent slices, where each slice can be decoded independently by different processor cores. This segmentation allows parallel processing while maintaining decoding accuracy, as each slice's decoding does not depend on others. The first core parses and allocates slices to the second core, enabling concurrent processing without compromising reliability.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If all video decoding functions are implemented in each core, then system resource utilization is improved, but device complexity increases

Engineering Contradiction:
Improvesystem resource utilizationVSAvoidcore functionality duplication
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal decoding model where the first core performs parsing and allocation functions, while the second core performs decoding and reconstruction functions. This multi-functional design allows different cores to specialize in specific tasks while maintaining overall system versatility, avoiding the complexity of duplicating all functions in each core.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Quantity of substance

If macroblocks are transferred sequentially from buffer to main memory, then memory bandwidth utilization is improved, but decoding time increases

Engineering Contradiction:
Improvememory bandwidth utilizationVSAvoiddecoding time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent implements continuous transfer of macroblocks from the auxiliary buffer to main memory during the decoding process. The second core continuously stores decoded macroblocks in the auxiliary buffer and transfers them to main memory without interruption, ensuring that memory bandwidth is fully utilized while maintaining continuous decoding operation without idle waiting time.

Inventive Principle:
Principle #20Continuity of useful action

4Ease of manufacture

If functional division is used to simplify multi-core implementation, then ease of implementation is improved, but parallel processing performance deteriorates

Engineering Contradiction:
Improveimplementation simplicityVSAvoidparallel processing performance
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent segments the decoding process into distinct functional units: the first core handles parsing and slice allocation, while the second core handles decoding and reconstruction. This functional division simplifies implementation by assigning specific responsibilities to each core, while simultaneously enabling parallel processing performance through independent operation of these segmented functions.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9131240B2Video decoding method and apparatus which uses double buffering
Publication Date: 2015.09.08 SAMSUNG ELECTRONICS CO LTD
  • US9131240B2 patent drawing
  • US9131240B2 patent drawing
  • US9131240B2 patent drawing

AI summary

A video decoding method and apparatus, the video decoding apparatus including: a decoder unit to control a video decoding operation; and a multi-core processor to perform the video decoding operation on an input bitstream by using the decoding unit, wherein the multi-core processor includes: a first core to parse the input bitstream into a plurality of slices and to allocate the slices; and a second core to receive one of the slices, to generate a plurality of macroblocks by decoding the received slice, to alternately store the macroblocks in first and second buffers included in an auxiliary memory thereof, to alternately transfer the macroblocks from the first and second buffers to a main memory, and to reconstruct an image for the macroblocks, wherein the macroblocks are transferred from one of the first and second buffers while the macroblocks are stored in the other one of the first and second buffers.