Video Decoder Memory Mapping for Parallel Frame Processing

The patent divides the memory access path into separate dedicated channels for each processing core, segmenting the system bus functionality. Each processing core has its own dedicated memory access channel, eliminating the need for all memories to share a common system bus, thus reducing system bus complexity while maintaining high memory bandwidth.

The patent introduces a memory controller as an intermediary component between the processing cores and memories. The memory controller manages memory access requests from multiple processing cores, coordinating access to multiple memories and eliminating the need for a complex system bus arbitration mechanism, thereby reducing system bus complexity.

The patent segments the memory access resources by assigning dedicated memory channels to each processing core. This segmentation allows simultaneous memory accesses from different processing cores without conflicts, as each core has its own dedicated access path, thereby maintaining high productivity while ensuring reliable memory access performance.

The patent implements preliminary memory access scheduling where the memory controller pre-manages access requests from multiple processing cores before actual memory access occurs. By coordinating and scheduling access requests in advance, the system prevents access conflicts and ensures smooth parallel processing operation.