Video Decoder Memory Segmentation for Latency Reduction
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Solution Overview
Problem
The existing video decoding systems experience increased latency due to the sequential nature of reading pixel data from memory devices, where data in different pixel lines are stored with discontinuous addresses, leading to extended latency as subsequent read requests are delayed until previous read operations are completed.
Innovation Solution
The use of multiple memory devices to store pixel lines of a reference picture allows for overlapping read operations, where a first set of pixel lines is stored in one memory device and a second set in another, enabling simultaneous reading of pixel blocks from both devices, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If multiple read requests are issued sequentially to read pixel data from different pixel lines, then the video decoder can access all required pixel data, but the latency increases due to sequential read operations
Solution Approach 1:
The patent divides the reference picture into multiple pixel line sets and stores them in separate memory devices. This segmentation allows independent read operations from different memory devices to proceed simultaneously, eliminating the sequential dependency that causes latency. Each memory device can serve its pixel line set without waiting for other reads to complete.
Solution Approach 2:
The patent introduces a spatial dimension by using multiple memory devices in parallel. Instead of accessing pixel data sequentially through a single memory device, the system accesses data from multiple memory devices simultaneously, adding a parallel dimension to the read operations and reducing overall latency.
2Loss of time
If data in different pixel lines are stored with discontinuous addresses in a single memory device, then memory access patterns become complex, but this causes extended latency as subsequent read requests are delayed
Solution Approach 1:
The patent segments the discontinuous pixel line data into separate memory devices, where each device stores a contiguous or organized set of pixel lines. This segmentation simplifies the address patterns within each memory device while maintaining the overall flexibility needed for video decoding, reducing the complexity of memory access management.
3Loss of time
If a single memory device stores all pixel lines of the reference picture, then memory device utilization is simple, but read operations must be sequential causing increased latency
Solution Approach 1:
The patent divides the single memory device into multiple memory devices, each storing a portion of the reference picture pixel lines. This segmentation enables parallel read operations from different memory devices, significantly reducing decoding latency while the system manages the increased device configuration through structured organization of pixel line data.
Data Source
AI summary
A video decoder organizes and stores pixel lines of a reference picture into first and second memory devices. The video decoder then reads portions of a pixel block from the first and second memory devices and processes such a pixel block for generating a subsequent picture. By reading from the first and second memory device with time overlap, latency is minimized for faster video decoding.