Video Decoder Parallel Processing JPEG2000 Bottleneck

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Solution Overview

Problem

Current JPEG2000 decoding methods are computationally intensive, making real-time processing challenging, especially for software decoders, and often require costly hardware or result in reduced picture quality by skipping data stream decoding.

Innovation Solution

A video decoder that decodes transformation coefficient blocks of different pictures on different computing kernels of a SIMD group simultaneously, exploiting parallelism to reduce decoding time and increase efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If JPEG2000 decoding is performed using conventional sequential methods, then decoding accuracy is maintained, but decoding speed is too slow to achieve real-time processing

Engineering Contradiction:
Improvedecoding speedVSAvoidreal-time processing capability
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent divides the picture sequence into multiple independent picture units that can be decoded separately. Each picture is further divided into transformation coefficient blocks that can be processed independently on different computing kernels, enabling parallel decoding without compromising the integrity of the decoding process

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces temporal parallelism by decoding multiple pictures from different time points simultaneously across different computing kernels. This adds a temporal dimension to the traditionally sequential decoding process, allowing multiple decoding operations to occur concurrently while maintaining causal dependencies within each individual picture

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If costly hardware is used to achieve real-time JPEG2000 decoding, then decoding speed is improved, but device complexity and cost increase

Engineering Contradiction:
Improvereal-time decoding capabilityVSAvoidhardware complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent designs a decoding system where a single computing device can handle multiple pictures simultaneously through parallel processing on different computing kernels. This multi-functional approach allows one device to perform what would traditionally require multiple dedicated hardware decoders, reducing overall system complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses computing kernels that can be instantiated multiple times across different processing units. These kernels represent copied functional units that execute the same decoding algorithm in parallel, enabling real-time performance through software-based parallelization rather than complex custom hardware

Inventive Principle:
Principle #26Copying

3Speed

If picture quality is reduced by skipping data stream decoding to increase speed, then decoding speed is improved, but picture quality deteriorates

Engineering Contradiction:
Improvedecoding speedVSAvoidpicture quality
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent performs complete decoding of all transformation coefficient blocks for each picture, rather than skipping parts of the data stream. By fully decoding multiple pictures in parallel, the system achieves both high speed and high quality, avoiding the trade-off present in selective decoding approaches

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP2591599B1Video decoder, method and computer program for parallel decoding of a sequence of pictures
Publication Date: 2017.02.01 FRAUNHOFER GESELLSCHAFT ZUR FORDERUNG DER ANGEWANDTEN FORSCHUNG EV
  • EP2591599B1 patent drawing
  • EP2591599B1 patent drawing
  • EP2591599B1 patent drawing

AI summary

A video decoder for decoding a sequence of pictures, each of which is coded into a plurality of transformation coefficient blocks, is configured to decode transformation coefficient blocks of different pictures on different computing kernels of a first SIMD group at the same time.