Video Decoder Pipeline Memory Layout for CU-Based Access Reduction
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Solution Overview
Problem
The increasing complexity of motion estimation and compensation in video decoders, particularly with new video compression standards like VVC, leads to higher memory access demands, necessitating an efficient memory access method to manage large volumes of digital data.
Innovation Solution
A video decoding device employing a decoder with multiple hardware blocks and pipeline memories to process data in pipeline units, storing unit data for each stage, and a memory to store decoded image data, utilizing CU size, next CU position, and scan type information to optimize memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If motion estimation and compensation methods are made more complicated to handle larger data volumes in new video compression standards, then video decoding capability is improved, but memory access requirements increase
Solution Approach 1:
The patent divides the decoding process into multiple pipeline stages (first pipeline stage, second pipeline stage, etc.) with each stage handling specific decoding tasks. Pipeline memories are segmented to store data for different stages separately, allowing parallel processing while managing memory access efficiently. This segmentation enables the system to handle complex video decoding operations without requiring excessive memory access by processing data in manageable chunks through dedicated pipeline units.
2Productivity
If pipeline memories are used to store unit data for each pipeline stage, then parallel processing efficiency is improved, but memory size requirements increase
Solution Approach 1:
The patent assigns specific storage functions to different pipeline memories based on their location in the pipeline. Each pipeline memory stores unit data relevant to its corresponding pipeline stage, creating a localized storage architecture. This local quality approach ensures that each memory component only needs to accommodate the data required for its specific stage, rather than requiring all memories to have uniform large capacity, thus reducing overall memory size while maintaining parallel processing efficiency.
3Quantity of substance
If data is processed in smaller pipeline units with detailed CU information, then memory usage is optimized, but processing complexity increases
Solution Approach 1:
The patent segments video data into coding units (CUs) with specific dimensions (e.g., 64x64, 32x32, 16x16 pixels) and processes them through dedicated pipeline units. Each pipeline unit handles specific CU types and scan patterns, breaking down the complex decoding task into manageable segments. This segmentation reduces memory usage by processing only relevant data portions at each stage while the modular pipeline architecture manages processing complexity through standardized handling of segmented data.
Solution Approach 2:
The patent employs multiple scan types (first scan type, second scan type, third scan type) with different parameter configurations for processing different CU dimensions and orientations. By changing scan parameters based on CU characteristics rather than using a fixed processing approach, the system optimizes memory usage for each specific data type while maintaining manageable processing complexity through parameter-based adaptation rather than structural complexity.
Data Source
AI summary
A video decoding device includes a decoder including plural hardware blocks that perform decoding processing on a bitstream by pipeline units and plural pipeline memories disposed between the hardware blocks and that store unit data, obtained through processing performed by pipeline units by the hardware blocks, for each pipeline stage, and a memory that stores image data obtained through decoding by the decoder.