Multi-core Video Decoder Stairstep Processing

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Solution Overview

Problem

Existing video decoding methods face challenges in increasing processing speed without enhancing hardware, particularly in mobile environments with size, power, and memory constraints, and struggle with low data locality and inefficient parallel processing due to data dependencies in video compression standards like H.264/AVC.

Innovation Solution

A multi-core processor system processes video data using a stairstep pattern, where a control core manages processing cores to improve cache hit rates by leveraging data locality and parallel processing, reducing interprocessor complexity and enhancing memory reuse.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If video decoding is performed in raster order to satisfy data dependencies, then data dependency requirements are met, but processing speed is limited and cache hit rate is low

Engineering Contradiction:

Improvedata dependency satisfactionVSAvoidprocessing speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The video frame is divided into multiple independent processing units called macroblocks, which are further segmented into 4×4 luma blocks and chroma blocks. This segmentation enables parallel processing of different blocks while maintaining data dependency requirements within each block, resolving the contradiction between sequential processing needs and parallel processing speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a new processing dimension by organizing macroblocks into multiple rows and columns that can be processed in parallel. Instead of single-threaded raster order processing, multiple processing elements work simultaneously on different rows or columns of macroblocks, achieving both data dependency satisfaction and improved processing throughput.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If processing hardware speed is increased to improve video decoding performance, then processing speed improves, but device size, power consumption, and memory usage increase

Engineering Contradiction:

Improvevideo decoding speedVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The system uses self-service by implementing a control mechanism that automatically manages the parallel processing elements. The control element dynamically activates or deactivates processing elements based on workload requirements, allowing the system to achieve high processing speeds only when needed, thereby reducing overall power consumption in mobile devices.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent changes the processing parameter from sequential to parallel by utilizing multiple processing elements that can operate simultaneously. This parameter change allows the system to achieve higher throughput without proportionally increasing power consumption, as the parallel elements can be managed efficiently through software control rather than requiring continuously high-power hardware.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If multiple processing cores are used to parallelize video decoding, then processing speed improves, but interprocessor complexity and synchronization requirements increase

Engineering Contradiction:

Improveparallel processing speedVSAvoidinterprocessor complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a control element as an intermediary that manages communication and synchronization between multiple processing elements. This intermediary handles the complexity of interprocessor coordination, allowing processing elements to work in parallel without direct complex interactions, thereby reducing overall system complexity while maintaining high processing speeds.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Reliability

If raster order processing is used to ensure data availability, then data dependency is satisfied, but cache hit rate decreases due to poor data locality

Engineering Contradiction:

Improvedata availabilityVSAvoidcache miss penalty

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-loading or pre-positioning data in cache memory before it is needed by processing elements. The control mechanism anticipates data requirements and ensures that data with good spatial locality is already in cache, reducing cache misses and improving processing efficiency without compromising data availability.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS8948267B1System and method of video coding using adaptive macroblock processing

Publication Date: 2015.02.03 SYNAPTICS INC

AI summary

An embodiment of the present invention includes a multi-core processor that processes video data. The control core controls a first processing core to process a first set of data blocks of an image frame according to a stairstep pattern. The control core detects, while the first processing core is processing the first set, that a triggering data block has been processed in the first set. The control core controls, while the first processing core is processing the first set, a second processing core to process a second set of data blocks using information from the triggering data block. By processing data blocks in the stairstep pattern, cache hit rate is improved, resulting in improved video decoder performance.