Video Decoding Deblocking Filter Parallel Processing
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Solution Overview
Problem
The existing deblocking process in video decoding is limited by data dependency, which restricts the use of dual-core or multi-core processors to perform parallel decoding of independent slices, leading to inefficiencies in processing ultra-high definition video bitstreams.
Innovation Solution
A method utilizing two processing units to apply an in-loop filter to block boundaries in separate regions of a video image concurrently, allowing for simultaneous deblocking of first and second block boundaries and re-applying the filter to second block boundaries adjacent to the region edge after filtering the first block boundaries, thereby reducing processing time and minimizing errors introduced by dummy data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single processor is used for video decoding with deblocking process, then processing accuracy is maintained, but processing speed and productivity are limited
Solution Approach 1:
The video image is divided into multiple independent regions (e.g., slices or parallel processing regions) that can be processed simultaneously by different processing units. Each processing unit applies the deblocking filter to its assigned region independently, enabling parallel processing while maintaining overall processing accuracy through coordinated boundary handling.
2Loss of time
If parallel processing is applied to multiple regions concurrently, then processing time is reduced, but errors may be introduced at region boundaries due to dummy data
Solution Approach 1:
Before initiating parallel deblocking processing across multiple regions, dummy data is pre-filled in boundary areas to enable all processing units to start simultaneously. After concurrent processing completes, a correction phase is performed where boundary regions are re-processed using actual neighboring data to eliminate errors introduced by the dummy data, ensuring final processing accuracy.
Solution Approach 2:
The system implements a feedback mechanism where the results of initial parallel processing are evaluated, and boundary regions showing errors from dummy data usage are identified and re-processed. This feedback loop ensures that any inaccuracies introduced during concurrent processing are corrected, maintaining overall reliability while preserving the speed benefits of parallel processing.
3Manufacturing precision
If sequential deblocking is applied to maintain accuracy, then processing precision is ensured, but productivity and throughput are reduced
Solution Approach 1:
The video frame is segmented into multiple independent processing regions that can be handled by separate processing units simultaneously. Each unit maintains deblocking accuracy for its region while parallel execution across units increases overall throughput, resolving the contradiction between precision and productivity.
Solution Approach 2:
Multiple processing units are merged to work concurrently on different regions of the same video frame. By coordinating their operations and implementing boundary correction mechanisms, the system achieves both high throughput (through parallelism) and high accuracy (through coordinated boundary handling).
Data Source
AI summary
A method and apparatus for deblocking process using multiple processing units are disclosed. The video image is divided into at least two regions. The in-loop filter is applied to block boundaries associated with said at least two regions using multiple processing units. The in-loop filter is re-applied to one or more second block boundaries adjacent to region edge between two regions after applying the in-loop filter to the first block boundaries adjacent to the region edge. Furthermore, at least a first portion of said applying the in-loop filter to the first block boundaries and a second portion of said applying the in-loop filter to the second block boundaries are performed concurrently. The multiple processing units may correspond to multiple processing cores within one processor chip.