Video Decoding Parallelizing Firmware Parsing with Hardware
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Solution Overview
Problem
Existing video decoding systems face limitations in reducing firmware operation time, which hinders the overall video decoding efficiency due to the dependency on decoder performance and varying bit-stream formats.
Innovation Solution
A video decoding apparatus and method that parallelize firmware operations, such as parsing header data, with hardware decoding operations by utilizing multiple bit-stream readers and a register buffer to pre-generate and store register sets for subsequent frames, allowing for simultaneous processing of multiple frames.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If firmware operation time is reduced by increasing RISC performance, then processing speed is improved, but the basic processing time cannot be significantly reduced and firmware operation time remains a bottleneck
Solution Approach 1:
The patent applies preliminary action by parsing header data and generating register sets for the next frame in advance, while the current frame is being decoded. This allows the firmware operation for the next frame to be completed before it is actually needed, eliminating the sequential bottleneck where firmware operation must wait for decoding to complete.
Solution Approach 2:
The patent implements continuity of useful action by maintaining parallel operations where the decoder continuously decodes current frames while the CPU simultaneously parses header data for subsequent frames. This eliminates idle time and ensures both components are continuously productive, transforming the previously sequential process into a continuous pipeline.
2Stability of the object's composition
If sequential processing is used where CPU parses header data before decoder decodes bit-stream, then processing order is maintained, but total decoding time increases due to inability to parallelize operations
Solution Approach 1:
The patent performs the header parsing and register set generation for the next frame in advance, during the decoding of the current frame. This preliminary action ensures that when the next frame needs to be decoded, all necessary firmware operations are already complete, allowing immediate hardware decoding without sequential waiting.
Solution Approach 2:
The patent transitions from one-dimensional sequential processing to two-dimensional parallel processing by overlapping firmware operations for frame N+1 with hardware decoding of frame N. This dimensional change in processing architecture allows simultaneous execution of different operations on different frames, eliminating the time penalty of sequential processing while maintaining correct processing order through proper timing control.
Data Source
AI summary
According to an example embodiment, a video decoding apparatus may be provided. The video decoding apparatus may include a central processing unit (CPU) configured to parse first header data included in an input bit-stream and generate a first register set based on the parsed first header data; and a decoder configured to decode the input bit-stream based on input parameters obtained through the first register set, wherein CPU is configured to parse second header data included in a second bit-stream of the input bit-stream of a second frame subsequent to the first frame while the decoder decodes a first bit-stream corresponding to the first frame.