Video Encoder Hardware Sharing for Multi-Standard Support
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Solution Overview
Problem
Existing video encoding/decoding methods, such as H.264, H.265, and AV1, face challenges in integrating multiple standards into a single video codec, leading to increased costs due to hardware duplication.
Innovation Solution
A video encoder design that includes a control circuit, data loading circuit, mode decision circuit, and entropy coding circuit, allowing for efficient encoding and decoding by managing multiple encoding modes and sharing hardware components across different standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple video encoding standards (H.264, H.265, AV1) are integrated into a single video codec, then versatility and adaptability are improved, but device complexity and manufacturing cost increase due to hardware duplication
Solution Approach 1:
The patent implements a universal video encoding hardware architecture that can operate in multiple encoding modes (H.264, H.265, AV1) using the same physical components. The control circuit dynamically configures the hardware resources based on the selected encoding standard, allowing one set of circuits to perform multiple functions that would traditionally require separate dedicated hardware for each standard.
Solution Approach 2:
The patent employs dynamic resource allocation and configuration where the control circuit adjusts the operating parameters and data flow paths based on the selected encoding mode. The hardware structure remains fixed but its functional configuration changes dynamically through control signals, enabling the same physical hardware to adapt to different encoding standards without physical reconfiguration.
2Adaptability or versatility
If multiple video encoding standards are integrated into a single video codec, then adaptability is improved, but manufacturing cost increases
Solution Approach 1:
The patent designs a universal hardware platform that eliminates the need for separate manufacturing lines for different encoding standards. By making the hardware multi-functional through software-controlled configuration, the manufacturing process is simplified to a single platform that can produce codecs supporting multiple standards, thereby reducing per-unit manufacturing costs.
Solution Approach 2:
The patent merges the functionality of multiple separate encoding standards into a single integrated hardware unit. Instead of manufacturing separate chips for H.264, H.265, and AV1, the patent combines all these functions into one chip that can be manufactured using the same process, reducing overall manufacturing complexity and cost.
3Ease of operation
If data loading circuit reads blocks sequentially from external memory, then ease of operation is improved, but productivity decreases due to waiting time
Solution Approach 1:
The patent implements a data loading circuit that pre-loads the next processing block from external memory into internal buffer memory while the current block is being processed. This preliminary action ensures that data is ready before it is needed, eliminating idle waiting time for the processing circuits and maintaining continuous operation without complicating the control logic.
Solution Approach 2:
The patent ensures continuous processing by overlapping data loading with processing operations. While the mode decision circuit processes one block, the data loading circuit simultaneously loads the next block, eliminating gaps in the processing pipeline and maintaining continuous useful action without requiring complex interdependent control mechanisms.
Data Source
AI summary
A video encoder is coupled to an external memory and configured to encode an input data to generate an output data. The input data includes a coding block. The video encoder includes a control circuit, a data loading circuit, a mode decision circuit, and an entropy coding circuit. The control circuit generates a start signal corresponding to the coding block. The data loading circuit reads the coding block from the external memory according to the start signal. The mode decision circuit processes the coding block according to the starting signal and generate an intermediate data. The entropy coding circuit generates the output data according to the intermediate data. In a video encoding mode, the control circuit further generates an indication signal indicating whether an image block of the coding block exists, and the mode decision circuit processes the image block according to the indication signal.