Hardware Video Encoder Parallel Mode Selection
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Solution Overview
Problem
High computational complexity in HEVC video encoding limits the ability of real-time encoders to efficiently select block sizes and modes, making it impractical for massive parallel processing and resulting in suboptimal coding efficiency.
Innovation Solution
A hardware-based video encoder that performs intra and inter mode selections in parallel, using parallel processing to compute pairs of prediction mode indices and rate-distortion values for different block sizes, reducing serial dependencies and computational load by approximating results typically obtained with reconstructed pictures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If extensively checking every possible block size is performed to achieve good coding efficiency, then coding efficiency is improved, but computational complexity increases significantly
Solution Approach 1:
The patent segments the exhaustive block size checking process into multiple stages: first checking only certain block sizes (e.g., 64x64, 32x32, 16x16) to generate initial rate-distortion values, then selectively checking other block sizes only when beneficial. This segmentation reduces the number of computations required while maintaining coding efficiency.
Solution Approach 2:
The patent applies partial action by not checking every possible block size exhaustively. Instead, it performs rate-distortion optimization only for a subset of block sizes in the first stage, and conditionally performs additional checks for other block sizes in subsequent stages, thereby reducing overall computational complexity while achieving sufficient coding efficiency.
2Manufacturing precision
If data correlations are used to achieve coding efficiency, then coding efficiency is improved, but serial dependencies increase making it unsuitable for massive parallel processing
Solution Approach 1:
The patent segments the encoding process into independent parallel stages: multiple search blocks can simultaneously compute rate-distortion values for different block sizes without serial dependencies, and the mode selection is performed independently for each coding unit. This enables massive parallel processing while maintaining coding efficiency through selective block size checking.
3Manufacturing precision
If rate-distortion optimization is performed with exact computations to achieve optimal block size selection, then coding efficiency is improved, but computational complexity becomes impractical for real-time encoders
Solution Approach 1:
The patent segments the rate-distortion optimization into two phases: a first pass that checks only certain block sizes to establish baseline rate-distortion values, and a second pass that conditionally checks other block sizes. This segmentation provides sufficiently accurate block size selection for real-time encoding without the impractical computational complexity of exhaustive exact optimization.
Solution Approach 2:
The patent performs partial rate-distortion optimization by limiting the first stage to checking only certain block sizes rather than all possible sizes. This partial optimization achieves practical block size selection accuracy for real-time encoders while avoiding the excessive computational complexity of complete optimization.
Data Source
AI summary
A hardware video encoder includes an intra search block operating on a source picture to produce pairs of intra prediction mode indices and rate-distortion values for different block sizes. The pairs of intra prediction mode indices and rate-distortion values for the different block sizes are computed in parallel based upon the source picture. An inter search block produces pairs of motion vectors and rate-distortion values for different block sizes. The pairs of motion vectors and rate-distortion values for the different block sizes are computed in parallel.