Video Latency Reduction via Independent Input Output Thread Slicing
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Solution Overview
Problem
Current computer video processing systems experience significant video latency, typically ranging from two to three frames, which is costly to reduce with hardware-based solutions and requires substantial infrastructure investment.
Innovation Solution
A computer-implemented method that creates independent input and output threads to split video frames into slices, allowing for simultaneous processing and synchronization with vertical blanking intervals to minimize latency, enabling latency reduction from two or three frames to one or two frames without significant hardware investment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional back buffer drawing method is used, then system robustness and simplicity are maintained, but video latency increases to two or three frames
Solution Approach 1:
The patent divides video frame processing into multiple independent slices (horizontal bands) that can be processed simultaneously. Each slice is handled by separate processing pipelines, allowing parallel execution and reducing overall processing time and latency while maintaining system simplicity.
Solution Approach 2:
The patent performs preliminary actions by pre-calculating slice boundaries, pre-allocating buffer memory regions, and pre-synchronizing with vertical blanking intervals before actual frame processing begins. This preparation enables faster real-time processing and reduces latency without increasing operational complexity.
2Loss of time
If hardware-based solutions are implemented to reduce video latency, then video latency can be reduced, but infrastructure investment cost increases significantly
Solution Approach 1:
The patent replaces hardware-based latency reduction mechanisms with software-based thread synchronization and slice processing algorithms. By using CPU/GPU software optimization instead of specialized hardware, the system achieves latency reduction without significant infrastructure investment.
Solution Approach 2:
The patent changes processing parameters by adjusting slice dimensions, thread priorities, and synchronization timing to optimize latency performance. These software parameter adjustments provide hardware-like performance improvements without the associated costs.
3Productivity
If frame processing waits for complete input frame reception, then processing accuracy is maintained, but processing speed decreases and latency increases
Solution Approach 1:
The patent segments the complete frame into slices that can be processed incrementally as they become available. This allows processing to begin before the entire frame is received, improving speed while maintaining accuracy through coordinated slice assembly and rendering.
Solution Approach 2:
The patent maintains continuous processing by overlapping frame reception, slice processing, and buffer swapping operations. Multiple threads work simultaneously on different stages of the pipeline, ensuring useful action continues without idle waiting while preserving frame integrity through synchronization.
Data Source
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AI summary
The invention relates to a computer-implemented method for reducing video latency and computer program product thereto for a computer video processing system. Two separate threads, an input thread and an output thread, are created and configured to run simultaneously and independently from each other. The input thread is configured to process video input frames that may be split into a plurality of input slices. The output thread is configured to process video output frames. The video output frames may also be split into a plurality of output slices.