Video Processing Pipelining for Buffer Reduction
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Solution Overview
Problem
Conventional video coding systems face high memory usage and processing inefficiencies due to the need for large buffers and high bandwidth in implementing deblocking filters and sample adaptive offset processing, particularly in hardware-based implementations, which increases system cost and power consumption.
Innovation Solution
The proposed solution treats deblocking filter (DF) and sample adaptive offset (SAO) processing as a single-stage pipelined structure, where the deblocking status is monitored to apply status-dependent SAO processing, allowing for partial or no SAO processing based on the deblocking status, reducing the need for extensive buffering and enabling earlier SAO processing by utilizing a pipeline buffer to store and process data efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deblocking filter and SAO processing are implemented as separate stages with extensive buffering, then processing completeness is improved, but memory usage and system cost increase
Solution Approach 1:
The patent combines deblocking filter (DF) and sample adaptive offset (SAO) processing into a single integrated hardware stage. The DF processing unit and SAO processing unit share common buffer resources and operate in a unified pipeline, eliminating the need for separate buffering structures. This merging reduces memory usage while maintaining complete processing functionality through coordinated operation of both processing units within the same stage.
2Reliability
If large buffers are used to store deblocked data for SAO processing, then data availability is improved, but bandwidth requirements and power consumption increase
Solution Approach 1:
The patent implements dynamic buffer management where the buffer size and allocation are adjusted based on real-time processing needs. The single-stage architecture allows the buffer to be shared and dynamically allocated between DF and SAO processing units, reducing the peak memory requirements compared to static separate buffering. This dynamic approach maintains data availability while reducing the overall buffer capacity needed, thereby lowering power consumption.
3Manufacturing precision
If separate DF and SAO processing stages are used, then processing thoroughness is improved, but processing latency increases
Solution Approach 1:
The patent enables continuous processing by eliminating the idle time between DF and SAO stages. The integrated single-stage architecture allows the SAO processing unit to immediately process output from the DF processing unit without waiting for complete buffer transfers or stage transitions. This continuous operation maintains thorough processing of both DF and SAO functions while significantly reducing the overall processing latency compared to separate staged implementations.
Data Source
Figure 1A
Figure 1B
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AI summary
A method and apparatus for applying DF processing and SAO processing to reconstructed video data are disclosed. The DF processing is applied to a current access element of reconstructed video data to generate DF output data and the deblocking status is determined while applying the DF processing. Status-dependent SAO processing is applied to one or more pixels of the DF output data according to the deblocking status. The status-dependent SAO processing comprises SAO processing, partial SAO processing, and no SAO processing. The SAO starting time for SAO processing is between the DF-output starting time and ending time for the current block. The DF starting time of a next block can be earlier than the SAO ending time of the current block by a period of t, where t is smaller than time difference between the DF-output starting time and the DF starting time of the next block.