Video Display Pixel Clock Adjustment for Jitter Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current video output technologies lack a software-based control mechanism to minimize the error between desired and actual presentation timestamps of video frames, leading to potential frame dropping or duplication, especially in real-time streams over sub-optimal networks, and require hardware genlock signals that are impractical for long-distance or bandwidth-limited distributions.
Innovation Solution
A computer-implemented method using a video display apparatus with a processor, memory, decoder, and frame buffer that adjusts the pixel clock based on time deltas between desired and actual display times, within user-adjustable latency thresholds, to control jitter and prevent frame errors, functioning as a sliding window to negate momentary timing issues without the need for hardware genlock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If hardware genlock signal distribution is used to synchronize video frames, then frame synchronization accuracy is improved, but device complexity and installation cost increase
Solution Approach 1:
The patent replaces the hardware genlock signal distribution network with a software-based control mechanism. The video display apparatus processor monitors presentation timestamps and adjusts video frame output timing through software control, eliminating the need for separate hardware synchronization signals while achieving comparable frame synchronization accuracy
Solution Approach 2:
The patent introduces a software intermediary layer (the control mechanism in the video display apparatus) that mediates between the incoming video stream and the display output. This software layer processes presentation timestamps and controls frame timing without requiring direct hardware genlock signals, simplifying the overall system architecture
2Reliability
If hardware genlock distribution network is implemented to ensure frame accuracy, then reliability of video synchronization is improved, but ease of manufacture and installation deteriorate
Solution Approach 1:
The video display apparatus performs self-synchronization by monitoring its own output timing and adjusting frame presentation based on presentation timestamps in the video stream. The processor automatically compensates for timing variations without requiring external genlock signals or complex hardware infrastructure, making the system both reliable and easy to install
3Ease of operation
If software control mechanism is used to adjust pixel clock and control jitter, then ease of operation is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies partial correction to the pixel clock, adjusting it in small increments based on timing errors detected in the video stream. Rather than making large adjustments, the system applies gradual corrections to maintain stability while achieving the necessary precision for frame synchronization
Solution Approach 2:
The control mechanism continuously monitors the actual presentation timestamps of video frames and uses this feedback to adjust the pixel clock timing. The processor compares desired presentation timestamps with actual output timing and dynamically adjusts the pixel clock to minimize timing errors, achieving precise control through iterative feedback
Data Source
AI summary
This disclosure describes a computer-implemented method for a control mechanism for video output. Additionally provided is a video stream that is generated from the video source and encoded by the video encoder, where the video stream further comprises one or more video frames with each video frame including a time stamp that includes timing and clocking information. Additionally provided is a video display apparatus that includes a video display apparatus processor, video display apparatus memory, video decoder, and a video frame buffer, where the video decoder decodes the encoded video stream, and the video display apparatus generates a pixel clock. Additionally provided is a desired latency threshold for displaying a first video frame with respect to a second video frame that includes an upper threshold limit and a lower threshold limit. The disclosed method includes the following steps that control jitter in the displayed video stream.