Video Signal PLL Clock Adjustment for Accurate Frame Capture
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Solution Overview
Problem
Image display apparatuses face challenges in correctly determining the format of inputted video signals and setting the frequency dividing ratio of the PLL circuit for generating a regenerative dot clock, leading to potential deviations in the frequency of the regenerative dot clock from the video signal, which can result in incorrect image display, especially with varying video signal formats and limited frame memory capacity.
Innovation Solution
An image display apparatus comprising a PLL unit, synchronization detecting unit, video detecting unit, and CPU unit that estimates the format of the inputted video signal, provisionally sets and recalculates the frequency dividing ratio of the PLL unit to match the capture width of the frame memory, and performs phase adjustments to ensure accurate frequency matching, converting the frequency dividing ratio to a multiple of 4 for optimal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the frequency dividing ratio of the PLL circuit is manually adjusted to match the dot clock frequency, then the frequency matching accuracy is improved, but the ease of operation deteriorates due to the cumbersome adjustment process
Solution Approach 1:
The system automatically detects the video signal format and self-adjusts the frequency dividing ratio without requiring manual user intervention. The CPU identifies the input signal characteristics and autonomously configures the PLL circuit parameters to achieve accurate frequency matching.
Solution Approach 2:
The system incorporates automatic detection and adjustment mechanisms that monitor the video signal characteristics and provide feedback to the PLL circuit configuration. This closed-loop approach ensures accurate frequency matching while eliminating manual adjustment requirements.
2Adaptability or versatility
If the frequency dividing ratio is incorrectly set due to lack of dot clock information in analog signals, then the adaptability to different video formats is improved, but the frequency matching accuracy deteriorates causing image display errors
Solution Approach 1:
The system performs preliminary detection of the video signal format characteristics before configuring the PLL circuit. By analyzing the analog signal properties in advance, the system pre-configures the appropriate frequency dividing ratio to ensure accurate frequency matching for the specific video format.
Solution Approach 2:
The system dynamically changes the frequency dividing ratio parameter based on the detected video signal format. The CPU identifies the signal characteristics and adjusts the PLL circuit parameters accordingly, enabling accurate frequency matching across different video formats without manual intervention.
3Productivity
If the horizontal display width is adjusted to match the frame memory capture width, then the productivity of image display is improved, but the measurement precision of the actual video signal width deteriorates due to rounding errors
Solution Approach 1:
The system applies a rounding rule that rounds up the calculated frequency dividing ratio to the nearest multiple of 4. This partial adjustment approach balances the need for integer-based PLL configuration with the desire to maintain accurate horizontal display width, accepting minimal deviation to achieve overall system compatibility.
Data Source
AI summary
A format of an inputted video signal is estimated to be based on the total number of vertical lines, and a frequency dividing ratio of a PLL unit is provisionally set at a predetermined value corresponding to the estimated format. Next, the frequency dividing ratio is calculated so that a measured value of a horizontal display width that is measured by a video detecting unit matches a capture width which is the horizontal display width capturable by a frame memory, and the calculated frequency dividing ratio is converted to a multiple of 4. A phase adjustment of the regenerative dot clock is performed against the video signal based on the converted frequency dividing ratio by using the regenerative dot clock generated by the PLL unit. Furthermore, the frequency dividing ratio is recalculated so that the measured value of the horizontal display width that is measured by the video detecting unit matches the capture width by using the regenerative dot clock after finishing the phase adjustment, and the calculated frequency dividing ratio is reset to the PLL unit.