Video Port Aggregator FPGA Buffer Asynchronous Latency
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Solution Overview
Problem
High-definition video systems with single digital signal processors face input/output resource limitations, preventing them from efficiently processing multiple video streams through a single digital video port.
Innovation Solution
An external logic field programmable gate array (FPGA) is used to implement a buffer that receives data from multiple inputs and transmits it to a single output, allowing for prioritization and encapsulation of data to manage asynchronous data flows and minimize latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single DSP processes multiple video streams through one digital video port, then I/O resource utilization is improved, but data processing capability and latency performance deteriorate due to insufficient input/output resources
Solution Approach 1:
An external FPGA-based buffer is introduced as an intermediary component between multiple video input channels and the single DSP video port. This buffer receives data from multiple asynchronous video channels, manages their data flows, and outputs to the DSP, thereby enabling the DSP to handle multiple video streams through a single port without sacrificing processing capability.
Solution Approach 2:
The system is divided into two functional parts: the external buffer that handles multiple input channels and the DSP that processes video data. This segmentation allows the buffer to manage the complexity of multiple asynchronous data streams while the DSP focuses on video processing, resolving the contradiction between I/O resource sharing and data processing capability.
2Productivity
If a buffer is used to aggregate multiple video channels, then data processing capability is improved, but latency increases due to buffering operations
Solution Approach 1:
The buffer implements dynamic prioritization of data channels, allowing high-priority channels to bypass buffering delays while low-priority channels wait in the buffer. This dynamic approach enables the system to maintain low latency for critical data streams while still aggregating multiple channels, thus resolving the contradiction between processing capability and latency.
Solution Approach 2:
The buffer performs preliminary buffering of low-priority data while high-priority data flows directly through, preparing data in advance for when it is needed. This preliminary action allows the system to maintain processing capability for multiple channels while minimizing latency for time-sensitive data.
3Productivity
If prioritization is implemented to manage asynchronous data flows, then data processing capability is improved, but device complexity increases
Solution Approach 1:
The external FPGA buffer serves as an intermediary that handles the complex prioritization and multiplexing logic externally, away from the DSP. This allows the DSP to maintain simple architecture while still achieving sophisticated data flow management through the external buffer's prioritization mechanisms.
Solution Approach 2:
The system uses channel identification markers or tags copied along with the video data to preserve channel information through the buffer. This copying approach enables the DSP to receive data from multiple channels through a single port while maintaining the ability to distinguish and process each channel independently, managing complexity through data duplication rather than complex internal routing.
Data Source
AI summary
A video port aggregator receives plural asynchronous video data streams. Corresponding input buffers generate video data and a status signal. A memory controller writes the video data in corresponding locations within an external memory. A channel triggers the memory controller to read data out of the external memory for transmission to a single video output port when said corresponding status signal indicates receipt of a predetermined portion of data. This read out of the external memory being faster than the writing. The channel sequencer triggers the memory controller to read data out of the external memory video data of a highest priority asynchronous video data stream having a received next portion of data.