Video Processing Subsystem Centralized Buffer Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing video and image processing systems face challenges with high data rates, heavy computation loads, and complex data flow, often requiring multiple passes to external memory and inefficient use of on-chip and external memory bandwidth due to limited silicon area and design complexity.
Innovation Solution
A hardware processing module architecture with a centralized buffer scheme and virtual addressing interface, allowing for efficient data flow management and reuse, utilizing a VBUSM CR that includes read and write buffers to optimize external memory bandwidth and design effort, and enabling modular connections for flexible data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a digital signal processor is used to provide imaging and video capability, then processing functionality is achieved, but data rate and computation load become excessively high
Solution Approach 1:
The video processing system is divided into multiple independent processing modules (motion estimation module, motion compensation module, DCT module, quantization module, etc.), each handling specific processing tasks. This segmentation distributes the computation load across multiple specialized units rather than overloading a single DSP, thereby maintaining high adaptability while managing computation load efficiently.
Solution Approach 2:
The patent introduces a temporal dimension through multi-frame buffering and pipelined processing. Multiple frames are held in buffer memory and processed in parallel across different stages simultaneously, transforming sequential processing into concurrent multi-dimensional processing. This increases throughput without proportionally increasing peak computation load on any single module.
2Speed
If on-chip memory is used for video processing, then fast access is achieved, but the memory size is not large enough to hold each frame
Solution Approach 1:
A buffer memory module serves as an intermediary between the fast on-chip memory and the slower external memory. The buffer memory (which can be implemented using on-chip resources) holds intermediate processing data and entire frames when not in active use, enabling fast access during critical processing stages while offloading storage requirements to external memory, thus resolving the capacity limitation without sacrificing access speed during processing.
Solution Approach 2:
The system uses multiple buffer memory modules (first buffer memory, second buffer memory) that can be selectively activated. While one buffer is being written to, another can be read from, enabling simultaneous read/write operations and maintaining fast access continuity. This temporal multiplexing allows the system to manage limited on-chip memory capacity while sustaining high-speed processing.
3Reliability
If multiple passes to external memory are performed, then processing completeness is achieved, but external memory bandwidth is inefficiently used
Solution Approach 1:
The buffer memory modules pre-load and store complete frames or processing intermediate results before they are needed by subsequent processing stages. This preliminary action eliminates the need for multiple sequential passes to external memory, as data is made available in advance in the buffer, ensuring processing completeness while requiring only single-pass efficient external memory access.
Solution Approach 2:
The pipelined processing architecture ensures continuous data flow through the processing stages. While one frame is being processed in the motion estimation module, another frame can be simultaneously processed in motion compensation, and a third in DCT, maintaining continuous useful action without idle cycles. This continuity maximizes external memory bandwidth utilization by keeping the memory interface actively transferring data throughout the processing cycle.
4Productivity
If frame processing is overlapped in a pipelined manner, then processing throughput is increased, but data flow complexity increases
Solution Approach 1:
The video processing system is divided into multiple independent processing modules (motion estimation module, motion compensation module, DCT module, quantization module, etc.), each handling specific processing tasks. This segmentation distributes the computation load across multiple specialized units rather than overloading a single DSP, thereby maintaining high adaptability while managing computation load efficiently.
Solution Approach 2:
A buffer memory module serves as an intermediary between the fast on-chip memory and the slower external memory. The buffer memory (which can be implemented using on-chip resources) holds intermediate processing data and entire frames when not in active use, enabling fast access during critical processing stages while offloading storage requirements to external memory, thus resolving the capacity limitation without sacrificing access speed during processing.
Data Source
AI summary
A video processing apparatus includes a plurality of processing modules, each performing an image processing function, and a central memory interface. The central memory interface accepts read and write memory the said plurality of processing modules and issues burst memory access requests to an external memory by gathering plural memory access requests from the processing modules.