Video Processor Bypass Control for Frame Rate Conversion

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Solution Overview

Problem

Existing electronic devices face challenges in efficiently processing video data due to high power consumption and delayed video playback when using frame rate conversion (FRC) for dynamic frame rate adjustment.

Innovation Solution

An electronic device and its operation method dynamically process the generation of interpolation frames through FRC, allowing for selective bypass of FRC processing based on a bypass control value related to video frames, and optimize video playback considering the content and playback situation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If frame rate conversion (FRC) processing is performed to dynamically adjust frame rate, then video playback quality is improved, but power consumption increases

Engineering Contradiction:
Improvevideo playback qualityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system dynamically adjusts the frame rate of video frames based on current playback conditions and content characteristics. Instead of using a fixed frame rate, the processor selectively applies frame rate conversion only when necessary, adapting the processing level to match actual playback needs and reducing unnecessary power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the frame rate parameter dynamically based on playback situation and video content. By adjusting this key parameter adaptively rather than maintaining a constant value, the system optimizes the balance between playback quality and power consumption.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If frame rate conversion (FRC) processing is performed to generate interpolation frames, then video playback quality is improved, but response time increases

Engineering Contradiction:
Improvevideo playback qualityVSAvoidresponse time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system applies frame rate conversion partially rather than universally. By performing FRC processing only on specific frames or under specific conditions rather than on all video frames, the system reduces the total processing time and improves response time while still maintaining adequate playback quality.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The processing level is dynamically adjusted based on playback conditions. When fast response is needed, the system reduces or skips FRC processing; when quality is prioritized and conditions permit, it applies full processing.

Inventive Principle:
Principle #15Dynamics

3Reliability

If frame rate conversion (FRC) processing is performed on all video frames, then video playback quality is improved, but processing efficiency decreases

Engineering Contradiction:
Improvevideo playback qualityVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system applies different processing levels to different video frames based on their specific characteristics and playback context. Instead of uniform processing, frames are selectively processed only when it adds value, improving overall processing efficiency while maintaining quality where needed.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Frame rate conversion is applied partially to only those frames that benefit from it, rather than processing all frames uniformly. This selective approach significantly improves processing efficiency by eliminating redundant operations on frames where FRC would provide minimal or no quality improvement.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12238452B2Electronic device for processing video and method for operating the same
Publication Date: 2025.02.25 SAMSUNG ELECTRONICS CO LTD
  • US12238452B2 patent drawing
  • US12238452B2 patent drawing
  • US12238452B2 patent drawing

AI summary

Disclosed is an electronic device including a display module and a processor. The processor is configured to obtain a first video frame and a bypass control value for the first video frame and determine whether to perform frame rate conversion (FRC) processing using the first video frame based on the bypass control value. Based on a determination that the bypass control value is set to a first value indicating bypass of the FRC processing, the processor is configured to display the first video frame. Based on a determination that the bypass control value is set to a second value indicating the FRC processing, the processor is configured to generate an interpolation frame using the first video frame and a second video frame after the first video frame, and display the first video frame, the interpolation frame, and the second video frame.