Video Processor Bypassing Pixel Clock Circuits
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Solution Overview
Problem
Conventional video processors require CRT legacy requirements, forcing non-CRT displays like LCDs to conform to pixel clock rates, even when it's not necessary, leading to inefficiencies and unnecessary circuitry.
Innovation Solution
A video processor architecture that provides a video signal directly related to a memory clock rate, independent of pixel clock rates, allowing for packetized data transmission at a link rate tied to the memory clock, eliminating the need for a CRT controller unit in non-CRT displays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional video processors force non-CRT displays to conform to pixel clock rates, then CRT legacy compatibility is maintained, but device complexity and power consumption increase unnecessarily
Solution Approach 1:
The patent extracts and removes the CRT controller unit and pixel clock generation circuits from the video processor when displaying on non-CRT displays. By eliminating these unnecessary components, the system achieves the same video output function without the complexity of CRT-specific circuitry, directly resolving the contradiction between maintaining compatibility and reducing device complexity.
Solution Approach 2:
The patent implements dynamic configuration where the video processor can operate in different modes: with CRT controller unit when CRT displays are detected, and without it when non-CRT displays are detected. This dynamic adaptation allows the system to maintain CRT legacy compatibility only when necessary, reducing circuitry complexity and power consumption for modern displays.
2Adaptability or versatility
If CRT controller unit and pixel clock generation circuits are included in all video processors, then CRT legacy compatibility is ensured, but power consumption increases for non-CRT displays
Solution Approach 1:
The video processor dynamically configures its operational mode based on the detected display type. When a non-CRT display is detected, the system disables the CRT controller unit and pixel clock generation circuits, thereby reducing power consumption while maintaining full display compatibility. This dynamic approach resolves the contradiction by adapting power usage to actual operational needs.
Solution Approach 2:
The patent applies different operational characteristics to different display types. For CRT displays, the full CRT controller functionality is activated; for non-CRT displays, only the essential video output functionality is maintained. This localized quality approach ensures compatibility across all display types while optimizing power consumption for each specific use case.
3Reliability
If pixel clock generation circuits are used for all displays, then consistent timing signals are provided, but unnecessary circuitry is included for non-CRT displays
Solution Approach 1:
The patent removes the pixel clock generation circuits from the video processor when operating with non-CRT displays. Since these displays do not require pixel clock timing signals, extracting this functionality eliminates unnecessary circuitry while maintaining reliable video output through alternative timing mechanisms appropriate for the specific display type.
Solution Approach 2:
The video processor is designed with universal functionality that can operate with or without the pixel clock generation circuits depending on the display type. This multi-functionality allows the same core video processing architecture to serve both CRT and non-CRT displays, resolving the contradiction between timing consistency and circuitry simplicity.
Data Source
AI summary
In a video processor unit, a method of providing a video data stream at a clock rate that is independent of a pixel clock rate. Receiving native video data from a video source at a native clock rate, storing the video data in a memory unit, reading selected portions of the video data at a memory clock rate, rasterizing the selected video data, packetizing the rasterized video data, sending the packetized video data to a display unit by way of a link at a link rate, wherein the link rate is directly related to the memory clock rate.