Video Processor Chip Memory Bandwidth Reduction via Segmented Buffers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current video processor chips require high bandwidth memory circuits to handle high-specification video data, leading to increased costs and complexity, as multiple processing circuits must read and write memory simultaneously for frame rate conversion and image compensation, which is insufficient for high-resolution and high-frame-rate applications.
Innovation Solution
A video processor chip with a memory circuit, frame rate converter circuit, and image compensation circuit that sequentially writes and reads frame data across multiple storage spaces, allowing frame rate conversion and image compensation without simultaneous data writing, thereby reducing memory bandwidth requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processing circuits read and write memory simultaneously for frame rate conversion and image compensation, then video processing capability is improved, but memory bandwidth requirement increases
Solution Approach 1:
The memory is divided into multiple independent buffer regions (first buffer, second buffer, third buffer) that can be independently accessed. This segmentation allows different processing circuits to operate on different buffer regions simultaneously, enabling parallel processing while reducing the bandwidth requirement on any single memory region.
Solution Approach 2:
Frame data is pre-stored in the memory buffers before processing. The first buffer stores previously written frame data that is ready for reading by the frame rate conversion circuit, eliminating the need for simultaneous read-write operations on the same memory region and reducing bandwidth requirements.
2Speed
If high bandwidth memory circuit is employed to process high specification video data, then video data transfer capability is improved, but cost and hardware complexity increase
Solution Approach 1:
The memory system is segmented into multiple buffers (first, second, third buffers) that can be independently managed. This allows the use of standard-speed memory circuits while achieving high data transfer capability through parallel access to multiple buffer regions, thereby reducing both cost and hardware complexity compared to using a single high-bandwidth memory circuit.
Solution Approach 2:
Instead of increasing bandwidth in the single-dimension time domain, the solution adds a spatial dimension by introducing multiple buffer regions that can be accessed in parallel. This dimensional expansion allows high data transfer capability to be achieved without requiring high-speed memory circuits, thus reducing hardware complexity and cost.
3Quantity of substance
If frame rate conversion and image compensation are performed using existing memory bandwidth, then memory bandwidth consumption is reduced, but processing speed decreases
Solution Approach 1:
The memory buffers are segmented and assigned to different processing functions: the first buffer is dedicated to frame rate conversion operations, while the second and third buffers support image compensation operations. This segmentation enables concurrent processing of frame rate conversion and image compensation without bandwidth contention, maintaining high processing speed while using existing memory bandwidth efficiently.
Solution Approach 2:
Multiple buffer regions act as intermediaries between the processing circuits and the memory system. These buffers decouple the read and write operations, allowing the frame rate conversion circuit to read from one buffer while data is written to another buffer, thereby enabling continuous processing without bandwidth conflicts and maintaining high processing speed.
Data Source
AI summary
A video processor chip includes a memory circuit, a frame rate converter circuit, and an image compensation circuit. The memory circuit includes first to third storage spaces. The frame rate converter circuit sequentially writes multiple frame data in video data to the first to the third storage spaces respectively, and reads second data in the frame data from the memory circuit to perform a frame rate conversion when first data in the frame data is written to the memory circuit. The second data is a previous frame data of the first data. The image compensation circuit reads third data in the frame data from the memory circuit when the frame rate converter circuit reads the second data, and performs an image compensation according to a difference between the second data and the third data. The third data is a previous frame data of the second data.