Video Processor Signal Synthesis for 2D and 3D Integration
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Solution Overview
Problem
Conventional video processors require two separate units to process 3D image signals, which increases complexity and cost, as they need to handle both 2D and 3D image signals simultaneously, and do not efficiently manage the switching between different monitor resolutions and image formats.
Innovation Solution
A video processor with a judgement section to determine the type of input signal, an image signal synthesis section to embed or separate left and right image signals in a side-by-side format, and an image processing section to apply processing to the synthesized signals, allowing for single-unit operation that handles both 2D and 3D image signals and switches between HD and SD resolutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two separate 2D video processors are used to process 3D image signals, then the image processing capability is sufficient, but the device complexity and cost increase
Solution Approach 1:
The patent merges the functionality of two separate 2D video processors into a single video processor that can handle both 2D and 3D image signals. The processor includes a signal type determination unit that identifies whether the input is 2D or 3D, and accordingly switches between processing modes. This consolidation reduces device complexity and cost while maintaining the capability to process both 2D and 3D signals effectively.
Solution Approach 2:
The single video processor is designed with multi-functionality to handle both 2D and 3D image signals through a unified architecture. The processor can dynamically adapt its processing mode based on the input signal type, eliminating the need for separate dedicated processors for 2D and 3D signals. This universal design reduces system complexity while preserving full processing capability for different signal types.
2Device complexity
If a single video processor handles both 2D and 3D signals, then the device complexity is reduced, but the clock management and resolution conversion become more complex
Solution Approach 1:
The video processor employs dynamic clock management that automatically adjusts the operating clock based on the input signal type and resolution requirements. The processor includes clock generation units that can dynamically switch between different clock frequencies and resolution conversion modes, making the complex clock and resolution management transparent to the user while maintaining optimal processing performance.
Solution Approach 2:
The patent introduces intermediary clock generation units and resolution conversion units that act as mediators between the input signals and the processing core. These intermediaries handle the complex clock synchronization and resolution conversion tasks, shielding the user from the complexity while enabling seamless switching between 2D/3D modes and different resolutions (HD/SD).
3Power
If dual processors are used for 3D processing, then the processing power is sufficient, but the connection management and output systems increase
Solution Approach 1:
The patent consolidates the processing power previously distributed across two separate processors into a single unified processor that maintains adequate processing capability for 3D signals. By merging the processing functions into one unit with intelligent signal routing and a single set of output connections, the system reduces connection management complexity while preserving sufficient processing power through efficient resource utilization and dynamic processing modes.
Data Source
AI summary
A video processor includes: a judgement section configured to judge whether an input is a 2D or 3D image signal; an LR synthesis section configured to embed left and right image signals into an image signal in a side-by-side format to output the signal if the input is the 3D image signal and configured to embed a 2D image signal into a position corresponding to one of the left and right in an image signal in a side-by-side format to output the signal if the input is the 2D image signal; and an image processing section configured to apply image processing to the image signal in the side-by-side format.