Master-Slave Video Reproduction System Synchronization
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Solution Overview
Problem
Existing digital signage systems face challenges in accurately synchronizing video signals across multiple display units due to high memory requirements and signal attenuation issues, leading to degraded video quality and timing inaccuracies.
Innovation Solution
A video information reproduction system that includes a master and slave device configuration, where each device has a storage unit, clock generator, decoder, and synchronization signal processor, allowing for precise synchronization of video signals through phase synchronization signals and counter value adjustments to maintain accurate timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If video data is stored in memory for multiple display units, then video synchronization can be achieved, but extremely large memory capacity is required
Solution Approach 1:
The patent divides the video data storage function across multiple independent reproduction devices, each with its own storage unit. Instead of one large centralized memory, each device stores its own video data locally, eliminating the need for extremely large shared memory capacity while maintaining synchronization through distributed architecture.
Solution Approach 2:
The patent introduces a reference clock signal as an intermediary mechanism to coordinate timing between distributed reproduction devices. This clock signal acts as a mediator that enables synchronization without requiring centralized memory storage, allowing devices to operate independently while maintaining temporal coherence.
2Reliability
If high-frequency clock signal is supplied from one reproduction unit to another, then synchronization can be achieved, but signal attenuation and waveform blunting occur
Solution Approach 1:
The patent generates independent reference clock signals at each reproduction device rather than transmitting a single high-frequency clock signal through wiring. Each device creates its own clock copy, eliminating signal attenuation and waveform blunting that would occur during transmission over distance.
Solution Approach 2:
The patent replaces the physical transmission of high-frequency electrical clock signals through wiring (which suffers from attenuation) with a distributed clock generation system. Each device independently generates its clock signal, substituting the mechanical/electrical transmission system with a distributed generation system that avoids transmission losses.
3Ease of operation
If PTS is used to adjust decoding timing, then video output can be controlled, but timing accuracy is degraded due to jitter and reference clock inaccuracies
Solution Approach 1:
The patent performs timing adjustment at the decoding stage using the reference clock signal, rather than relying on PTS (Presentation Time Stamp) values that are applied after decoding. By controlling the decoding timing itself with an accurate reference clock, the system achieves better timing precision before the video data is output.
Solution Approach 2:
The patent uses the reference clock signal as a feedback mechanism to continuously adjust and maintain accurate timing throughout the decoding and output process. This closed-loop approach ensures that timing drift and jitter are corrected in real-time, maintaining high timing accuracy.
4Device complexity
If multiple reproduction units decode video data independently, then system complexity is reduced, but video signal synchronization is degraded
Solution Approach 1:
The patent provides each reproduction device with an identical reference clock signal, creating equipotential timing conditions across all devices. Each device operates independently with the same timing reference, ensuring that all decoding and output operations occur at the same temporal potential, thus achieving synchronization without complex inter-device coordination.
Data Source
AI summary
A video information reproduction system includes first and second video information reproduction devices. A first synchronization signal processor of the video information reproduction device as a master device generates a phase synchronization signal including a first vertical synchronization signal and a first counter value and sends it to the second video information reproduction device. A second synchronization signal processor of the second video information reproduction device as a slave device compares the phase synchronization signal with a second vertical synchronization signal on the basis of a second video clock signal, and a second clock generator changes the frequency of a second decode reference clock signal on the basis of a result of the comparison.