Video Resizer Using Circular Buffers to Reduce Latency

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Solution Overview

Problem

Real-time video applications face latency issues due to intermediate buffering in fractional decimation processes, which hinder efficient resizing of video frames.

Innovation Solution

Implementing a cascade of horizontal and vertical polyphase resizers with minimal buffering, utilizing a DMA controller and circular buffers to reduce latency and memory requirements, allowing for sub-frame latency and efficient resizing of video data by a scaling factor expressible as a ratio of two integers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If intermediate frame buffering is used for fractional decimation, then resizing accuracy is improved, but latency increases

Engineering Contradiction:
Improveresizing accuracyVSAvoidlatency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent segments the buffering requirement into two parts: a small circular buffer for horizontal resizing and a minimal line buffer for vertical resizing. This segmentation allows each buffer to be optimized for its specific purpose, achieving accurate fractional decimation without requiring a full frame buffer, thus reducing latency while maintaining resizing precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent processes video data by separating horizontal and vertical resizing operations into different dimensional stages. Horizontal resizing is performed first on individual lines using a circular buffer, then vertical resizing is performed on the horizontally resized data using a line buffer. This dimensional separation enables accurate fractional decimation without requiring all lines to be buffered simultaneously, reducing latency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If full frame buffering is used for vertical resizing, then resizing completeness is improved, but memory usage increases

Engineering Contradiction:
Improveresizing completenessVSAvoidmemory usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent divides the buffering requirement into two separate, smaller buffers: a circular buffer for horizontal resizing operations and a line buffer for vertical resizing operations. This segmentation eliminates the need for a large frame buffer, reducing memory usage from O(width×height) to O(width + height), while still ensuring complete and accurate resizing through the coordinated operation of both buffers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a two-stage resizing process where horizontal resizing is performed first on individual lines, then vertical resizing is performed on the intermediate results. This dimensional separation allows vertical resizing to operate on a single line at a time rather than requiring the entire frame to be buffered, dramatically reducing memory requirements while maintaining resizing completeness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If line buffers are implemented as FIFO buffer on serial processor, then processing flexibility is improved, but memory requirements increase

Engineering Contradiction:
Improveprocessing flexibilityVSAvoidmemory requirements
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent implements a dynamic circular buffer that automatically recycles buffer space as data is processed. The circular buffer uses wraparound addressing to reuse memory locations, allowing the buffer to maintain a small fixed size while dynamically adapting to the continuous stream of video data. This dynamic approach provides processing flexibility equivalent to larger static buffers but with minimal memory requirements.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8111331B2Image resizer and resizing method
Publication Date: 2012.02.07 CISCO TECHNOLOGY INC
  • US8111331B2 patent drawing
  • US8111331B2 patent drawing
  • US8111331B2 patent drawing

AI summary

An apparatus embodiment is operative to scale video and includes an input buffer coupled to a real time source of video data and configured to hold a number of lines of video, a horizontal resizer coupled to the input buffer to resize lines of image data, outputting horizontally scaled line(s) to an intermediate buffer configured to store a number of lines. The apparatus has a vertical resizer coupled to the intermediate buffer configured to output vertically and horizontally resized lines of image data. At any given time, some of the lines in the input buffer are scheduled using the DMA controller for replacement via DMA by lines generated by the source of video data, and some or all of the remaining lines in the input buffer are available for processing by the horizontal resizer. A sufficient number of lines are available in the intermediate buffer, such that in operation, the intermediate buffer need not introduce latency.