Video Scaling Circuit Using Stable Crystal Clock
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Solution Overview
Problem
Existing video display scaling devices face issues with unstable output frames due to PLL inaccuracies, leading to insufficient line buffers and incorrect image output, especially under conditions like fast forward or slow motion, where the input clock can be unstable and cause deviations in the output clock.
Innovation Solution
A circuit and method that use a stable crystal clock to generate the output clock, rather than relying on the input clock, and incorporate an error correction mechanism to adjust the output image points, ensuring stable sync signals and minimizing the number of line buffers required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the input clock is used to generate the output clock via PLL, then the frame rate is maintained equal, but the output clock deviates from the desired display frequency due to PLL inaccuracies
Solution Approach 1:
A stable crystal clock is introduced as an intermediary to generate the output clock signal, replacing the direct use of the unstable input clock. This mediator provides frequency accuracy while allowing the input clock to maintain frame rate consistency through the scaling operation.
2Ease of manufacture
If the output clock changes with the input clock to maintain frame rate equality, then the scaling operation is simplified, but the output clock becomes unstable under fast forward, fast rewind, and slow motion conditions
Solution Approach 1:
The clock generation function is segmented into two independent parts: the input clock handles frame rate timing for scaling simplicity, while the stable crystal clock handles output frequency generation for stability. This separation allows each component to optimize for its specific function without compromising the other.
3Device complexity
If a limited number of line buffers is used to reduce memory requirements, then the device complexity is reduced, but the buffers become insufficient when output clock deviation occurs
Solution Approach 1:
The stable crystal clock acts as a mediator that decouples the line buffer timing from the unstable input clock. This allows the limited number of line buffers to operate correctly by providing a stable timing reference that prevents buffer overflow and underflow conditions.
Data Source
AI summary
A scaling device for video displays includes a limited number of line buffers and produces stable output frames by using a stable clock source to produce the output image clock. The scaling device further includes an error counter for determining an error between an ideal output line length and an actual line length and an error accumulator for keeping a running total of all output line length errors. The error accumulator can signal when the total line error for a given frame is greater than one, indicating that an additional output point should be added to the blanking area of that output line.