Video Server Sync Signal Distribution for CPU Synchronization

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Solution Overview

Problem

In video server apparatuses, ensuring high-quality image playback across multiple CPUs in a broadcasting system is challenging due to the complexity of synchronizing timers and the lack of effective failure detection and recovery mechanisms, particularly in high-speed asynchronous data transmission environments.

Innovation Solution

A video server apparatus is configured with a memory, recorder, decoder, controller, synchronizer, and sync signal transmitter, utilizing timers and time managers to generate and distribute sync signals in frame units, and includes decision functions to detect synchronization errors and recover data, ensuring reliable playback even in the presence of failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If timers are synchronized among multiple CPUs using conventional methods, then synchronization is achieved, but the inter-CPU process becomes complicated

Engineering Contradiction:
Improvesynchronization among CPUsVSAvoidinter-CPU process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a sync signal transmitter as an intermediary component that generates and distributes synchronization signals to all CPUs. This mediator approach centralizes the synchronization function, eliminating the need for complex peer-to-peer timer synchronization protocols between CPUs, thus simplifying the inter-CPU process while maintaining reliable synchronization.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If high-precision timers are incorporated in each processor, then synchronization precision is improved, but the apparatus cost increases

Engineering Contradiction:
Improvesynchronization precisionVSAvoidapparatus cost
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the synchronization signal generation function into a single dedicated sync signal transmitter component, while all CPUs use standard timers that reference this common signal source. This consolidation approach achieves high synchronization precision without requiring expensive high-precision timers in each CPU, thereby reducing overall apparatus cost.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If redundancy systems are implemented for failure recovery, then reliability is improved, but the apparatus complexity increases

Engineering Contradiction:
Improvefailure recovery capabilityVSAvoidsystem structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the sync signal transmitter monitors CPU operation status and automatically triggers redundancy switching when failures are detected. This feedback-based approach enables reliable failure recovery through redundancy systems while minimizing apparatus complexity by using automated detection and switching logic rather than complex manual intervention systems.

Inventive Principle:
Principle #23Feedback

4Speed

If data is transmitted in real-time at frame level over high-speed asynchronous bus, then data transmission speed is improved, but synchronization control becomes difficult

Engineering Contradiction:
Improvedata transmission speedVSAvoidsynchronization control
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by generating and distributing synchronization signals before actual data transmission occurs. The sync signal transmitter pre-establishes timing references for all CPUs, enabling them to properly synchronize their data processing and transmission operations even over asynchronous buses, thus maintaining frame-level real-time performance while simplifying synchronization control.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8997168B2Video server apparatus and synchronization control method
Publication Date: 2015.03.31 KK TOSHIBA
  • US8997168B2 patent drawing
  • US8997168B2 patent drawing
  • US8997168B2 patent drawing

AI summary

According to one embodiment, a video server apparatus includes a memory, a recorder, a decoder, a controller, a synchronizer, a sync signal transmitter and a time manager. The synchronizer generates sync signals in frame unit. The sync signal transmitter distributes the sync signals generated by the synchronizer in frame unit, to the memory, the recorder, the decoder and the controller. Each of the memory, recorder, decoder and controller includes a time manager. The time manager manages the sync signals distributed.