Video Server Unified Control Cycle for Interlaced and Progressive Signals
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Solution Overview
Problem
Current video servers face increased processing load and complexity when handling both interlaced and progressive video signals, as they require different control cycles, leading to potential interference and difficulty in managing output timing.
Innovation Solution
A video server configuration where the CPU generates memory information tables for interlaced and progressive video signals based on specific control cycles, allowing the playback device to read and output signals according to these cycles, thereby reducing CPU load and simplifying playback control by unifying the control cycle to 33 ms for both types of signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the video server controls progressive video signals at intervals of 16.5 ms (half the interlaced cycle), then the playback timing precision for progressive signals is improved, but the processing load on the CPU doubles
Solution Approach 1:
The patent merges the control cycles of interlaced and progressive video signals by having the CPU control both types at the same 33 ms interval. The playback control unit generates field output timing signals at 33 ms intervals for interlaced signals and at 16.5 ms intervals for progressive signals, but the CPU itself operates at the unified 33 ms cycle, thereby reducing processing load while maintaining precise playback timing for both signal types.
2Reliability
If the video server implements separate control cycles for interlaced (33 ms) and progressive (16.5 ms) video signals, then the playback timing for each signal type is optimized, but the software complexity increases
Solution Approach 1:
The patent implements a universal control cycle of 33 ms that serves both interlaced and progressive video signals. The playback control unit is designed to generate field output timing signals adaptable to different signal types using the same base cycle, eliminating the need for separate control pathways and reducing software complexity while maintaining optimized playback timing for each signal type.
3Device complexity
If the video server uses a unified control cycle of 33 ms for both interlaced and progressive video signals, then the processing load and software complexity are reduced, but the playback timing precision for progressive signals may be affected
Solution Approach 1:
The patent segments the control function into two levels: the CPU operates at a unified 33 ms cycle for managing both signal types, while the playback control unit generates differentiated field output timing signals at 33 ms intervals for interlaced signals and 16.5 ms intervals for progressive signals. This segmentation allows the system to maintain low complexity at the CPU level while achieving high timing precision at the signal output level.
Data Source
AI summary
According to one embodiment, a video server reads a first type of video signal for one screen from a memory address related to a screen based on a clock pulse if first information in order to read the first type of video signal from the memory device with the first predetermined time interval and the clock pulse are received, and reads a second type of video signal for integral multiple screens from the playback controller in order to read the second type of video signal from the memory device with a changing point of the clock pulse level if the second information from the playback controller in order to read the second type of video signal from the memory device with the first predetermined time interval and the clock pulse are received.