Video Signal Processing Circuit Contention Control
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Solution Overview
Problem
Conventional video processing circuits experience display errors due to contention between writing pixel data in the GRAM and reading pixel data equivalent to one scanning line, leading to incorrect bit values being stored in the latch circuit, resulting in display errors.
Innovation Solution
A video signal processing circuit with a control unit that delays the reading of pixel data during contention periods, allowing for re-reading of pixel data after a predetermined delay, ensuring accurate data transfer and preventing display errors. This control unit includes a delay unit and a monitoring unit to adjust the delay time based on contention occurrences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pixel data is written in the GRAM during the memory update period, then the pixel data can be updated in real-time, but contention occurs between writing and reading operations causing display errors
Solution Approach 1:
The patent applies preliminary action by detecting potential contention between write and read operations before it occurs. The control unit monitors the timing of write operations to the GRAM and anticipates when read operations might be affected, allowing it to preemptively adjust the read timing or insert delay cycles to prevent display errors before they happen.
Solution Approach 2:
The patent implements feedback by having the control unit continuously monitor the state of the GRAM and the timing of write operations. Based on this feedback information about ongoing write operations, the control unit dynamically adjusts the read operation timing to avoid contention, ensuring reliable data reading while maintaining real-time update capability.
2Reliability
If the reading operation is delayed to avoid contention, then display errors are prevented, but the processing time increases
Solution Approach 1:
The patent applies partial action by implementing delay cycles only when and where contention is detected, rather than delaying all read operations uniformly. The control unit selectively inserts delay cycles based on the actual timing of write operations, applying the time penalty only partially to the specific read operations that would otherwise conflict with write operations.
3Productivity
If the latch circuit reads pixel data during the memory update period, then the display refresh rate is maintained, but incorrect bit values are stored due to simultaneous write operations
Solution Approach 1:
The control unit acts as an intermediary between the GRAM and the latch circuit. It monitors write operations to the GRAM and uses this information to mediate the timing of read operations to the latch circuit, inserting delay cycles or adjusting timing to ensure that read operations occur only when the GRAM data is stable and correct.
Data Source
AI summary
A display error occurs upon contention between writing of pixel data in a GRAM and reading of pixel data representing a scanning line including pixels which correspond to the pixel data above. Pixel data corresponding to pixels representing a scanning line stored in a latch circuit is displayed on a display panel, and when contention occurs between writing of pixel data in a GRAM and reading of pixel data corresponding to pixels representing a scanning line to the latch circuit from the GRAM, a controller delays reading of the pixel data corresponding to the pixels representing the scanning line and controls so as to perform reading of the pixel data corresponding to the pixels representing the scanning line to the latch circuit from the GRAM once again.