Video Synchronization Circuit Using Digital Phase-Locked Loop
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Solution Overview
Problem
Synchronizing multiple video displays with different line and pixel resolutions while maintaining low jitter is challenging, especially when only a vertical sync reference signal is available, leading to potential discontinuities and simulator sickness in real-time simulation applications.
Innovation Solution
A system and method using a digitally controlled circuit to generate a phase-locked intermediate frequency signal from the input vertical sync signal, converted into a pixel clock by an analog phase lock loop circuit, allowing for synchronization of multiple video streams with flexible line and pixel resolutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard PLL line-locking is used to synchronize video circuits, then synchronization is achieved, but discontinuities occur when line and pixel counts differ
Solution Approach 1:
The synchronization process is divided into two independent stages: first, vertical sync signals from multiple video circuits are combined and locked using a digital phase-locked loop; second, the locked vertical sync is used to generate horizontal sync signals through frequency multiplication. This segmentation allows each stage to optimize for its specific function, avoiding the discontinuities that occur when trying to lock both vertical and horizontal syncs simultaneously with differing line and pixel counts.
Solution Approach 2:
A vertical sync signal serves as an intermediary that bridges the multiple video circuits with different line and pixel counts. By first locking all circuits to this common vertical sync reference and then deriving their individual horizontal syncs from it, the system eliminates the need for direct mutual synchronization between circuits with incompatible parameters, thereby preventing discontinuities.
2Device complexity
If vertical sync only reference is used for synchronization, then device complexity is reduced, but synchronization precision deteriorates
Solution Approach 1:
The system performs preliminary frequency multiplication of the vertical sync signal to create an intermediate frequency signal before using it to generate the final pixel clock. This preliminary action prepares the signal in advance, allowing the subsequent analog PLL to lock onto a higher frequency reference that enables more precise pixel timing while maintaining the simplicity of vertical-sync-only input.
Solution Approach 2:
The system changes the frequency parameter of the vertical sync signal by multiplying it by a factor of 4 through the digital phase-locked loop and frequency multiplication stage. This parameter change transforms the low-frequency vertical sync into a higher-frequency intermediate signal that can be more precisely converted into the pixel clock, thereby improving precision without adding complexity to the input requirements.
3Speed
If high frequency pixel clock is generated from low frequency vertical sync, then pixel clock frequency is improved, but jitter increases
Solution Approach 1:
An intermediate frequency signal serves as a mediator between the low-frequency vertical sync and the high-frequency pixel clock. The digital phase-locked loop first generates this intermediate signal at a frequency four times the vertical sync frequency, providing a higher-frequency reference that reduces the multiplication factor needed in the final stage and thereby minimizing jitter accumulation.
Solution Approach 2:
The system replaces the traditional mechanical/frequency-division approach with a digital phase-locked loop that uses phase detection and frequency multiplication. This substitution allows for more precise frequency conversion with lower jitter by using digital phase accumulation and comparison mechanisms rather than analog frequency division, enabling high-frequency pixel clocks to be derived cleanly from low-frequency vertical sync signals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively synchronizes multiple video streams with low jitter, ensuring seamless display across multiple screens and maintaining alignment with external system equipment, enhancing the realism and effectiveness of simulation environments.
Implementation Method 1
a digitally controlled circuit configured to generate a phase locked intermediate frequency signal which is higher than the frequency of the input vertical sync signal
Implementation Method 2
an analog phase lock loop circuit configured to convert the intermediate frequency signal into a pixel clock
Data Source
AI summary
A vertical synchronization circuit for synchronizing multiple video streams using an input vertical sync signal. The circuit includes a digital phase lock loop circuit configured to generate an intermediate frequency signal based on the input vertical sync signal and an analog phase lock loop circuit configured to convert the intermediate frequency signal into a pixel clock. They system further includes a counter configured to generate output synchronization signals based on the pixel clock.