Video Processing Device Synchronization Signal Disturbance Handling
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Solution Overview
Problem
Conventional video processing devices experience communication disturbances due to synchronization signal disturbances, leading to video display issues and unstable communication with the microcomputer, particularly when switching between video input sources or modes, as they require time to detect the presence or absence of a video signal for generating communication timing signals.
Innovation Solution
A video processing device with a synchronization signal detecting unit and a control unit that outputs the input vertical synchronization signal as the output signal when detected at a predetermined cycle, and if not detected before the cycle elapses, generates a new output signal after the cycle, reducing direct output of the signal and stabilizing communication and video display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the video processing device directly outputs the input vertical synchronization signal as the output signal, then the response speed is improved, but the stability of video display and communication deteriorates when the synchronization signal is disturbed
Solution Approach 1:
The video processing device performs preliminary detection of the vertical synchronization signal before outputting it. The detection unit checks whether the signal meets predetermined conditions (such as proper cycle timing) before allowing it to be output. This preliminary action prevents disturbed signals from causing instability while maintaining fast response when signals are valid.
Solution Approach 2:
The invention introduces a detection unit as an intermediary between the input and output of the vertical synchronization signal. This intermediary component analyzes the signal characteristics and controls whether the signal should be output, acting as a mediator that filters out disturbed signals while passing valid signals through, thus resolving the contradiction between speed and stability.
2Reliability
If the video processing device waits to detect the vertical synchronization signal at a predetermined cycle, then the stability is improved, but the response time deteriorates
Solution Approach 1:
The detection cycle is made dynamic rather than fixed. The detection unit can adjust its detection timing based on whether the signal is currently valid or disturbed. When the signal is valid, detection occurs at predetermined cycles for stability. When disturbed, the detection unit can trigger immediate detection or switch to self-generating timing signals, reducing response time while maintaining stability during normal operation.
3Speed
If the video processing device uses the input vertical synchronization signal for communication timing, then the communication speed is improved, but the communication stability deteriorates when the synchronization signal is disturbed
Solution Approach 1:
The detection unit serves as an intermediary that controls the use of the input vertical synchronization signal for communication timing. It monitors signal quality and determines whether the signal should be used for timing communication. When the signal is valid, it enables fast communication using the input signal. When disturbed, it prevents the use of the disturbed signal, thereby maintaining communication stability while preserving the ability for fast communication when conditions are good.
Data Source
AI summary
There is provided a video processing device capable of reducing the influence of a disturbance of an input vertical synchronization signal. When the synchronization signal detecting unit detects an input of the input-side vertical synchronization signal at a predetermined cycle, the synchronization signal control unit outputs the input-side vertical synchronization signal, which has been input, as an output-side vertical synchronization signal, and, when the synchronization signal detecting unit detects an input of a next input-side vertical synchronization signal before the predetermined cycle elapses after the output of the output-side vertical synchronization signal, a next input-side vertical synchronization signal input before the predetermined cycle elapses is not output as a next output-side vertical synchronization signal, and an input-side vertical synchronization signal input further next is output as the next output-side vertical synchronization signal.