View Pruning for Integrated Circuit Clock Tree Synthesis

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Solution Overview

Problem

The complexity of large integrated circuit designs requires significant resources to verify all acceptable combinations of variables, leading to inefficient computing and long analysis times due to the need to simulate numerous operating conditions, or 'views', during the design process.

Innovation Solution

The method of 'view pruning' identifies a smaller set of 'dominant views' that represent relevant information, allowing only these views to be analyzed during clock tree synthesis, thereby reducing the number of views and target slews considered, which improves computing efficiency and reduces runtime.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all operating conditions (views) are simulated during circuit design verification, then verification completeness is improved, but computing resources and analysis time are excessively consumed

Engineering Contradiction:
Improveverification completenessVSAvoidcomputing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts and identifies a smaller subset of dominant views from the complete set of operating conditions. By separating the essential views that contribute most to verification quality from the redundant ones, the system achieves effective verification with reduced computational burden. The dominant view identification process extracts only the necessary views for meaningful analysis.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter of view selection from considering all operating conditions to considering only dominant views based on specific criteria. This parameter change in the verification approach transforms the problem from exhaustive simulation to targeted analysis of critical views, significantly improving computing efficiency while maintaining verification effectiveness.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If all operating conditions (views) are simulated during circuit design verification, then verification completeness is improved, but analysis time is excessively increased

Engineering Contradiction:
Improveverification completenessVSAvoidanalysis time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts a minimal set of dominant views that capture the essential verification requirements. By removing redundant views from the analysis set, the system reduces analysis time from simulating all operating conditions to simulating only the critical dominant views, achieving significant time savings without compromising verification quality.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies partial action by performing verification on a subset of dominant views rather than all views. This partial verification approach is sufficient to achieve the desired verification completeness while avoiding the excessive time cost of full verification, demonstrating that complete analysis of all views is not necessary for effective verification.

Inventive Principle:
Principle #16Partial or excessive action

3Manufacturing precision

If a large number of views are analyzed during clock tree synthesis, then design verification thoroughness is improved, but computing resources are excessively consumed

Engineering Contradiction:
Improvedesign verification thoroughnessVSAvoidcomputational complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent extracts and identifies dominant views that represent the critical design scenarios. By focusing computational resources on these extracted dominant views rather than all possible views, the system achieves thorough verification of critical aspects while avoiding the computational complexity of analyzing every possible view.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the verification parameter from analyzing all views to analyzing only dominant views identified through specific criteria. This parameter change reduces the computational complexity from exponential growth with the number of views to a manageable analysis of a smaller dominant subset, maintaining verification thoroughness for critical design aspects.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10643019B1View pruning for routing tree optimization
Publication Date: 2020.05.05 CADENCE DESIGN SYST INC
  • US10643019B1 patent drawing
  • US10643019B1 patent drawing
  • US10643019B1 patent drawing

AI summary

Electronic design automation systems, methods, and media are presented for view pruning to increase the efficiency of computing operations for analyzing and updating a circuit design for an integrated circuit. One embodiment involves accessing a circuit design stored in memory that is associated with a plurality of views, selecting a first view of the plurality of view for view pruning analysis, and identifying a plurality of input values for the first view of the plurality of views. Random nets are generated based on the views, view inputs, and pruning thresholds. Certain views are then selected as dominant based on a comparison of the output slews different nets and views. Subsequent analysis is then performed and used to update the design without using the pruned views (e.g., using the selected dominant views).