Virtualized L1 Cache Partitioning for VIPT Synonym Coherency
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Solution Overview
Problem
Existing integrated circuit designs face challenges with virtually indexed physically tagged (VIPT) caches due to the issue of synonyms, where the same physical cache block appears at two different virtual indexes, leading to inefficiencies and pipeline impacts when cache sizes exceed virtual memory page sizes.
Innovation Solution
The L1 cache is split into multiple logical L1 caches sharing the same physical implementation, with an outer memory system resolving ownership conflicts and disambiguating synonyms using a coherence protocol, allowing the L1 cache to hold two shared synonyms without increasing pipeline complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the L1 cache size is increased beyond virtual memory page size, then cache capacity and performance are improved, but synonym conflicts increase causing pipeline stalls and complexity
Solution Approach 1:
The L1 cache is segmented into multiple logical L1 caches, each responsible for a specific portion of the virtual address space. This segmentation allows the cache to handle synonyms by directing them to different logical caches, eliminating pipeline stalls while maintaining large total cache capacity.
2Reliability
If multiple logical L1 caches are implemented, then synonym handling is improved, but hardware resources and area increase
Solution Approach 1:
Multiple logical L1 caches are merged into a single physical L1 cache structure. The logical caches share the same physical storage resources, tag arrays, and data arrays, with differentiation achieved through logical partitioning based on virtual address bits. This merging approach provides synonym resolution capabilities while minimizing additional hardware area overhead.
3Object-generated harmful factors
If L1 cache way size is limited to virtual memory page size, then synonym conflicts are avoided, but cache capacity and efficiency are reduced
Solution Approach 1:
The solution moves from limiting cache capacity in one dimension (way size) to managing synonyms in another dimension (logical cache partitioning). By introducing the dimension of logical cache identification and using virtual address bits to select between logical caches, the system achieves both large total capacity and effective synonym handling without constraining individual way sizes.
Data Source
AI summary
Systems and methods are disclosed for virtualized caches. For example, an integrated circuit (e.g., a processor) for executing instructions includes a virtually indexed physically tagged first-level (L1) cache configured to output to an outer memory system one or more bits of a virtual index of a cache access as one or more bits of a requestor identifier. For example, the L1 cache may be configured to operate as multiple logical L1 caches with a cache way of a size less than or equal to a virtual memory page size. For example, the integrated circuit may include an L2 cache of the outer memory system that is configured to receive the requestor identifier and implement a cache coherency protocol to disambiguate an L1 synonym occurring in multiple portions of the virtually indexed physically tagged L1 cache associated with different requestor identifier values.