Virtual Address Block Registration for Network I/O Latency
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Solution Overview
Problem
Computer systems employing network communications links face significant performance degradation due to the time-consuming process of memory registration and deregistration for each I/O operation, especially since different virtual address areas are used for different operations and these tasks are resource-intensive.
Innovation Solution
The solution involves assigning a block of virtual addresses for use with a computer network communications link, registering the entire block prior to I/O operations, and performing I/O operations without the need for buffer copies or memory registration and deregistration per operation, allowing direct access to physical memory through low latency and OS bypass mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory registration and deregistration are performed for each I/O operation, then data transfer correctness is ensured, but system performance deteriorates due to time-consuming registration tasks
Solution Approach 1:
The patent applies preliminary action by registering a large block of virtual addresses (e.g., 4GB) in advance before I/O operations begin, rather than registering individual addresses for each operation. This pre-registration eliminates the need for repeated registration tasks during data transfer operations, significantly reducing overhead and improving system performance while ensuring data transfer correctness.
2Adaptability or versatility
If different virtual address areas are used for different I/O operations, then data transfer flexibility is improved, but the number of registration tasks increases
Solution Approach 1:
The patent merges multiple individual virtual address registrations into a single block registration. By consolidating numerous small virtual address areas into one large contiguous block (e.g., 4GB), the system maintains the flexibility to perform different I/O operations while reducing the number of registration tasks from many individual operations to just one bulk registration.
3Speed
If OS bypass mechanisms are used, then data transfer speed is improved, but memory management complexity increases
Solution Approach 1:
The patent introduces a mapping mechanism as an intermediary between the OS bypass data transfer path and physical memory. This mapping layer allows fast OS bypass transfers while managing the complexity of virtual to physical address translation, enabling high-speed data transfer without directly burdening the OS while maintaining proper memory management.
Data Source
AI summary
Systems and methods for performing data input/output (I/O) operations using a computer network communications link are described. A method may include assigning a block of virtual addresses for usage with at least one computer network communications link. The method may also include registering the entire block of virtual addresses prior to an operating system partition performing I/O operations using the at least one computer network communications link, wherein registering comprises setting a plurality of virtual page frame numbers of the block of virtual addresses to point to distinct pages of physical memory. In some embodiments, one or more I/O operations may be performed using the at least one computer network communications link and the registered block of virtual addresses.