Virtual-Address Cache Invalidation for Multi-Page Sizes
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Solution Overview
Problem
Managing virtual-address caches in multi-core processors with multiple memory page sizes poses challenges due to the mismatch between translation granularity (memory pages) and caching granularity (memory blocks), leading to over-invalidation issues when handling translation lookaside buffer invalidations.
Innovation Solution
Implementing a virtual-address cache management system that stores memory blocks with associated page sizes in the translation lookaside buffer, allowing for precise invalidation of cache entries by comparing selected bits of the invalid virtual address with corresponding entries using codes representing different page sizes, thereby reducing over-invalidation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If translation lookaside buffer invalidation is performed using traditional methods, then translation correctness is maintained, but cache over-invalidation occurs leading to increased cache miss rate and reduced performance
Solution Approach 1:
The patent segments the invalidation process by introducing page size codes that divide the cache into multiple segments corresponding to different page sizes. When a TLB invalidation occurs, only the cache segment matching the invalidation's page size is invalidated, rather than invalidating the entire cache. This segmentation allows precise invalidation of only the affected cache lines while preserving others, thus maintaining translation correctness while improving cache hit rate by reducing unnecessary invalidations.
Solution Approach 2:
The patent applies local quality by associating different page size codes with different cache entry characteristics. Each cache entry is tagged with a page size code that matches its corresponding TLB entry's page size. This allows the invalidation mechanism to selectively invalidate only those cache entries with matching page size codes, applying the invalidation locally to the specific affected region rather than globally across the entire cache, thereby preserving cache hits in unaffected regions.
2Adaptability or versatility
If multiple page sizes are supported in the translation lookaside buffer, then memory addressing flexibility is improved, but the complexity of managing virtual-address caches increases
Solution Approach 1:
The patent implements universality by designing a unified cache management mechanism that handles multiple page sizes through a single page size code field. The same cache structure and invalidation logic can accommodate different page sizes (e.g., 4KB, 16KB, 64KB) by simply using different code values, rather than requiring separate cache structures for each page size. This multi-functional approach maintains addressing flexibility while managing complexity through a standardized handling method.
Solution Approach 2:
The patent introduces page size codes as an intermediary between the TLB and the virtual-address cache. These codes act as mediators that carry page size information from TLB entries to cache entries, enabling the cache management logic to understand and handle different page sizes without requiring complex direct mapping or multiple specialized structures. The intermediary codes simplify the interface between translation mechanisms and cache management.
3Ease of operation
If cache invalidation is performed without page size information, then the invalidation process is simple, but precision is lost leading to unnecessary cache entries being invalidated
Solution Approach 1:
The patent applies preliminary action by pre-associating page size codes with cache entries during cache population, before invalidation operations occur. When a cache line is loaded, its corresponding page size code is stored alongside the cache data. This preliminary tagging enables rapid and precise matching during invalidation operations, allowing the system to quickly identify and invalidate only the affected cache entries without requiring complex analysis at invalidation time, thus maintaining simplicity while achieving precision.
Data Source
AI summary
A translation lookaside buffer stores information indicating respective page sizes for different translations. A virtual-address cache module manages entries, where each entry stores a memory block in association with a virtual address and a code representing at least one page size of a memory page on which the memory block is located. The managing includes: receiving a translation lookaside buffer invalidation instruction for invalidating at least one translation lookaside buffer entry in the translation lookaside buffer, where the translation lookaside buffer invalidation instruction includes at least one invalid virtual address; comparing selected bits of the invalid virtual address with selected bits of each of a plurality of virtual addresses associated with respective entries in the virtual-address cache module, based on the codes; and invalidating one or more entries in the virtual-address cache module based on the comparing.