Virtual Address Cache Access via Synonym Tracking Circuit
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Solution Overview
Problem
Current computer architectures face inefficiencies in cache access due to the need for physical address translation, which increases latency and energy consumption when using virtual addresses, and the challenge of aliasing in virtual address spaces, which reduces cache capacity and introduces consistency issues.
Innovation Solution
The implementation of a cache architecture that allows direct access using virtual addresses by tracking synonyms through a synonym tracking circuit, which includes an Active Synonym Signature (SS) and Address Remapping Table (ART), enabling efficient conversion of virtual addresses to a key virtual address for cache access without requiring TLB lookups, thereby reducing latency and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If physical address translation is used for cache access, then address mapping accuracy is improved, but access latency and energy consumption increase
Solution Approach 1:
The patent pre-establishes synonym relationships in the ART table before cache access occurs. When a virtual address is accessed, the system checks the ART table in advance to determine if synonym aliases exist, allowing the cache to be accessed directly using the original virtual address without requiring physical address translation through TLB, thus reducing access latency while maintaining mapping accuracy
Solution Approach 2:
The patent introduces an Address Remapping Table (ART) as an intermediary structure that stores pre-computed synonym relationships. This ART table acts as a mediator between virtual addresses and cache access, eliminating the need for traditional physical address translation while maintaining correct address mapping. The synonym tracking circuit uses the ART table to quickly determine whether synonym aliases exist for a given virtual address
2Measurement precision
If physical address translation is used for cache access, then address mapping accuracy is improved, but energy consumption increases
Solution Approach 1:
The system pre-computes and stores synonym relationships in the ART table before actual cache access occurs. This preliminary action allows the cache to be accessed directly using virtual addresses without triggering energy-consuming physical address translation through TLB, significantly reducing energy consumption while maintaining accurate address mapping through the pre-established synonym information
Solution Approach 2:
The ART table serves as an energy-efficient intermediary that provides address mapping functionality without requiring full physical address translation. By using the ART table to check for synonym relationships, the system avoids the energy-intensive TLB lookup process while maintaining accurate address mapping
3Reliability
If virtual address aliasing is prohibited to maintain cache consistency, then data consistency is improved, but cache capacity and locality of reference exploitation decrease
Solution Approach 1:
The patent implements a feedback mechanism where the synonym tracking circuit continuously monitors and updates the ART table with synonym relationships discovered during cache access. This feedback loop allows the system to dynamically adapt to virtual address aliasing patterns, maintaining data consistency by identifying and handling synonyms while preserving cache capacity to store diverse virtual addresses that map to the same physical locations
Data Source
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AI summary
A computer architecture provides a memory cache that is accessed not by physical addresses by virtual addresses directly from running processes. Ambiguities that can result from multiple virtual addresses mapping to a single physical address are handled by dynamically tracking synonyms and connecting a limited number of virtual synonyms mapping to the same physical address to a single key virtual address that is used exclusively for cache access.