Virtual-Address Store-to-Load Forwarding for Lower Pipeline Delay
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Solution Overview
Problem
Processor pipelines face challenges in efficiently handling memory hazards due to long delays in executing memory operations and the need for complex condition checks for store-to-load forwarding, particularly in out-of-order architectures, which increase circuit area and power consumption.
Innovation Solution
Implementing store-to-load forwarding using virtual addresses to identify memory hazards earlier in the pipeline, leveraging miss status holding registers to reduce indirection and parallelize condition checks, thereby reducing delay and circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If store-to-load forwarding is implemented using physical addresses, then memory hazard detection accuracy is improved, but pipeline delay increases due to address translation requirements
Solution Approach 1:
The patent performs store queue tag comparison using virtual addresses earlier in the pipeline before physical address translation is complete. This preliminary hazard detection using virtual addresses allows the system to identify potential forwarding opportunities without waiting for the slower physical address translation to finish, thereby reducing pipeline delay while maintaining detection capability
Solution Approach 2:
The patent introduces virtual address as an intermediary for early hazard detection. Instead of directly using physical addresses which require translation, the system uses virtual addresses as a mediator to perform preliminary comparisons in the store queue, enabling earlier detection without compromising the accuracy of final physical address-based forwarding decisions
2Reliability
If complex condition checks are performed for store-to-load forwarding in out-of-order architectures, then forwarding accuracy is improved, but circuit area and power consumption increase
Solution Approach 1:
The patent segments the hazard detection process into multiple stages: initial virtual address-based filtering in the store queue, followed by physical address verification later in the pipeline. This segmentation allows complex condition checks to be distributed across different pipeline stages rather than concentrated in one location, reducing the circuit area required at any single stage while maintaining overall forwarding accuracy
Solution Approach 2:
The patent performs a partial check using virtual addresses early in the pipeline to filter out non-candidate stores, and then performs the complete physical address verification only for the subset of loads that pass the initial filter. This partial action approach reduces the overall circuit area and power consumption by avoiding full condition checks for all load-store pairs, while still maintaining forwarding accuracy through the subsequent verification step
3Speed
If store-to-load forwarding is implemented, then load execution speed is improved, but circuit complexity increases
Solution Approach 1:
The patent performs preliminary virtual address comparison in the store queue to identify potential forwarding candidates before the load instruction reaches the execution stage. This preliminary action enables faster load execution by pre-preparing forwarding information and reducing the computational burden at the critical execution stage, while the added complexity is distributed to earlier pipeline stages where it has less impact on overall circuit complexity
Solution Approach 2:
The patent merges the hazard detection function with the existing store queue structure by integrating virtual address comparison logic into the store queue tag comparison mechanism. This merging allows the system to implement store-to-load forwarding without adding completely separate detection circuits, thereby improving load execution speed while minimizing the increase in overall circuit complexity through resource sharing and functional integration
Data Source
AI summary
Systems and methods are disclosed for store-to-load forwarding for processor pipelines. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor pipeline; a store queue that has entries associated with respective store instructions that are being executed, wherein an entry of the store queue includes a tag that is determined based on a virtual address of a target of the associated store instruction; and store-to-load forwarding circuitry that is configured to: compare a first virtual address of a target of a first load instruction being executed by the load unit to respective tags of one or more entries in the store queue; select an entry of the store queue based on a match between the first virtual address and the tag of the selected entry; and forward data of the selected entry in the store queue to be returned by the first load instruction.