64-bit Virtual Address Metadata Bit Canonicality Check
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Solution Overview
Problem
Existing processors face challenges in allowing 64-bit virtual addresses to include metadata bits without causing canonicality checks to fail, which restricts the ability to expand address spaces and efficiently use memory.
Innovation Solution
The processor is modified to include one or more metadata bits in the most significant bits of a 64-bit virtual address, and circuitry is implemented to perform canonicality checks that do not fail due to non-canonical values of these metadata bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 64-bit virtual addresses include metadata bits in the most significant bits, then the ability to store metadata and expand address space is improved, but canonicality checks fail due to non-canonical values of metadata bits
Solution Approach 1:
The patent segments the 64-bit virtual address into distinct functional regions: metadata bits (bits 63-57) and address bits (bits 56-0). This segmentation allows the metadata portion to be treated separately from the address portion, enabling the canonicality check to focus only on the address bits while the metadata bits can contain arbitrary values including non-canonical patterns.
Solution Approach 2:
The patent applies different quality requirements to different parts of the virtual address. The metadata bits (bits 63-57) are allowed to have any value including non-canonical patterns, while the address bits (bits 56-0) must satisfy canonicality requirements. This local differentiation resolves the contradiction by allowing metadata flexibility without compromising address validity.
2Reliability
If canonicality checks are performed on all bits of 64-bit virtual addresses, then address validity is ensured, but metadata storage capability is restricted
Solution Approach 1:
The canonicality check is segmented to apply only to the address portion (bits 56-0) of the virtual address, while the metadata portion (bits 63-57) is excluded from the canonicality requirement. This selective application maintains address validity while enabling metadata storage.
Solution Approach 2:
Different quality standards are applied locally: the address bits must be canonical to ensure valid memory addressing, while the metadata bits can be non-canonical to provide flexible data storage. This local quality differentiation resolves the contradiction between reliability and adaptability.
Data Source
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AI summary
Techniques to allow use of metadata in unused bits of virtual addresses are described. For example, a processor of an aspect comprises a model specific register having a bit to store a first bit value, a code segment register having a bit to store a second bit value, and circuitry to perform a canonicality check on a 64-bit virtual address. The 64-bit virtual address has bit positions 56:0 to store an address. If the first bit value and the second bit value are set to binary one, a third bit value is set to binary one, and the 64-bit virtual address is used for a data access, the canonicality check on the 64-bit virtual address will not fail due to bits stored in bit positions 62:57 of the 64-bit virtual address being non-canonical.