Virtual Address Prefetching Across Memory Page Boundaries

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional prefetching techniques struggle to effectively predict memory requests using virtual addresses due to the changing virtual-to-physical mapping, limiting the length of prefetchable strides and leading to increased cache misses.

Innovation Solution

A method that monitors memory requests associated with load instructions, detects patterns in virtual addresses by comparing differences between recent memory requests, and uses this information to prefetch data across different memory pages by maintaining a table of recent virtual addresses and their differences, allowing for strides of any practicable length.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional prefetching uses physical addresses to detect patterns, then prefetching accuracy is improved within a single memory page, but prefetching effectiveness deteriorates when crossing memory page boundaries due to virtual-to-physical mapping changes

Engineering Contradiction:
Improvepattern detection accuracyVSAvoidprefetching effectiveness across memory pages
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent uses virtual addresses as a copy or representation of the actual memory access patterns, avoiding the need to translate to physical addresses. By working directly with virtual addresses that maintain their sequential pattern across page boundaries, the system can detect strides and prefetch effectively without being disrupted by virtual-to-physical mapping changes at page boundaries

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent introduces virtual addresses as an intermediary that bridges the gap between the application's memory access patterns and the physical memory system. By using virtual addresses as the intermediate representation for pattern detection, the system can identify strides across multiple physical pages without being affected by the virtual-to-physical translation process

Inventive Principle:
Principle #24Intermediary (Mediator)

2Stability of the object's composition

If prefetching is limited to within single memory pages, then mapping stability is improved, but prefetch stride length is limited to 4 KB boundaries

Engineering Contradiction:
Improvevirtual-to-physical mapping stabilityVSAvoidprefetch stride length
Core Design Contradiction:
Stability of the object's compositionVSLength of moving object

Solution Approach 1:

The patent shifts the dimension of operation from physical address space (constrained by 4 KB page boundaries) to virtual address space (which can span multiple pages). By detecting patterns and calculating strides in virtual address space, the system can prefetch across arbitrary distances without being constrained by physical page boundaries, while the virtual-to-physical mapping remains stable for each individual virtual address

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Measurement precision

If the prefetcher translates virtual addresses to physical addresses for pattern detection, then physical address patterns can be identified, but the complexity of address translation increases and prefetching across pages becomes difficult

Engineering Contradiction:
Improveaddress pattern detectionVSAvoidaddress translation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts the address translation step from the pattern detection process. Instead of translating virtual addresses to physical addresses and then detecting patterns, the system directly detects patterns in virtual addresses. This extraction eliminates the complexity of address translation while maintaining the ability to identify memory access patterns and calculate strides

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10977176B2Prefetching data to reduce cache misses
Publication Date: 2021.04.13 MARVELL ASIA PTE LTD
  • US10977176B2 patent drawing
  • US10977176B2 patent drawing
  • US10977176B2 patent drawing

AI summary

A first memory request including a first virtual address is received. An entry in memory is accessed. The entry is selected using information associated with the first memory request, and includes at least a portion of a second virtual address (first data) and at least a portion of a third virtual address (second data). The difference between the first data and the second data is compared with differences between a corresponding portion of the first virtual address and the first data and the second data respectively. When a result of the comparison is true, then a fourth virtual address is determined by adding the difference between the first data and the second data to the first virtual address, and then data at the fourth virtual address is prefetched into the cache.