Rule-Based Virtual Address Translation for Packet Switching

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Solution Overview

Problem

Packet switching devices face latency issues in retrieving forwarding information due to the size of forwarding tables, affecting their ability to handle a large number of devices or connections efficiently.

Innovation Solution

Implementing rule-based virtual address translation methods that match virtual addresses against predetermined rules to convert them into lookup addresses, allowing data access operations across multiple memory units, including internal and external memories, optimizing storage and access based on storing description parameters such as power-of-two translation page size and striping of data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If forwarding tables are made larger to handle more devices or connections, then the number of devices or connections that can be handled increases, but the latency in retrieving forwarding information increases

Engineering Contradiction:
Improvenumber of devices or connections that can be handledVSAvoidlatency in retrieving forwarding information
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent segments the forwarding table into multiple memory units (first memory unit and second memory unit) with different storage characteristics. Frequently accessed forwarding information is stored in the first memory unit with faster access, while less frequently accessed information is stored in the second memory unit. This segmentation allows the system to handle more connections overall while maintaining low latency for critical lookups by prioritizing access to the first memory unit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by differentiating the storage characteristics of different portions of the forwarding table. The first memory unit provides high-speed access for frequently accessed entries, while the second memory unit provides capacity expansion for less frequently accessed entries. This creates a non-uniform storage architecture where different regions of the forwarding table have different access properties optimized for their specific usage patterns.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If the size of forwarding tables is increased to handle more connections, then the number of devices or connections that can be handled increases, but the forwarding rate of the packet switching device decreases

Engineering Contradiction:
Improvenumber of devices or connections that can be handledVSAvoidforwarding rate
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the forwarding table into multiple memory units with different performance characteristics. The first memory unit stores frequently accessed forwarding information with faster access speeds, while the second memory unit stores less frequently accessed information. This segmentation enables the system to expand the overall forwarding table size to handle more connections while maintaining high forwarding rates for critical packets by prioritizing access to the first memory unit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements local quality by creating different storage regions with different access properties. The first memory unit provides high-speed access optimized for frequently accessed forwarding entries, while the second memory unit provides capacity for less critical entries. This differentiated storage architecture allows the system to maintain high forwarding rates for most packets while accommodating a larger total number of connections.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9256548B2Rule-based virtual address translation for accessing data
Publication Date: 2016.02.09 CISCO TECHNOLOGY INC
  • US9256548B2 patent drawing
  • US9256548B2 patent drawing
  • US9256548B2 patent drawing

AI summary

In one embodiment, rule-based virtual address translation is performed for accessing data (e.g., reading and/or writing data) typically stored in different manners and/or locations among one or more memories, such as, but not limited to, in packet switching devices. A virtual address is matched against a set of predetermined rules to identify one or more storing description parameters. These storing description parameters determine in which particular memory unit(s) and/or how the data is stored. Thus, different portions of a data structure (e.g., table) can be stored in different memories and/or using different storage techniques. The virtual address is converted to a lookup address based on the identified storing description parameter(s). One or more read or write operations in one or more particular memory units is performed based on the lookup address said converted from the virtual address.