Virtual Addresses for Action Memories in Hardware Forwarding

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Solution Overview

Problem

In packet processing hardware, moving data from one SRAM to another requires reconfiguration of match and action entries, leading to inefficiencies due to fixed page numbers and large action entries that exceed memory width, resulting in data redundancy and increased addressing complexity.

Innovation Solution

Assigning virtual page numbers to data sets in SRAMs allows for seamless movement of data between memories without reconfiguration, using a coding scheme to efficiently specify action entry distribution across multiple memories and direct addressing for match entries, reducing the need for extensive virtual page number listing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If data is moved from one unit memory to another, then memory optimization is improved, but reconfiguration of match and action entries is required

Engineering Contradiction:
Improvememory optimizationVSAvoidreconfiguration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the memory system into multiple unit memories (SRAMs) that can be independently configured and moved. Each unit memory can be dynamically assigned to store different sets of match or action entries, allowing the system to optimize memory usage by moving data between units without requiring reconfiguration of the entire memory system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic memory allocation where unit memories can be moved and reassigned during operation. The system dynamically adjusts which unit memory stores which data set, enabling optimization of memory performance while maintaining flexibility in data placement without fixed assignments.

Inventive Principle:
Principle #15Dynamics

2Ease of operation

If fixed page numbers are used for addressing, then addressing simplicity is improved, but data movement between memories requires reconfiguration

Engineering Contradiction:
Improveaddressing simplicityVSAvoiddata movement flexibility
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent introduces a virtual page number dimension that overlays the physical memory structure. Instead of directly addressing physical memory locations, the system uses virtual page numbers that can be mapped to any physical unit memory. This additional addressing dimension allows data to be moved between physical memories while maintaining simple, unchanged virtual addresses.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces virtual page numbers as an intermediary layer between the match/action entries and the physical unit memories. This intermediary abstraction allows the system to decouple the logical addressing scheme from the physical memory layout, enabling data movement without reconfiguration of address references.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of substance

If action entries are stored in multiple unit memories, then data redundancy is reduced, but addressing complexity increases

Engineering Contradiction:
Improvedata redundancyVSAvoidaddressing complexity
Core Design Contradiction:
Loss of substanceVSDevice complexity

Solution Approach 1:

The patent segments large action entries across multiple unit memories, storing different portions of the same action entry in different physical memory units. This segmentation reduces data redundancy by allowing the system to store only the necessary portions of action entries in the memory system, while the virtual addressing mechanism handles the distribution across multiple units.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses virtual page numbers to add an addressing dimension that simplifies access to action entries distributed across multiple unit memories. Instead of requiring complex physical addressing that accounts for the distribution across memories, the virtual page number system provides a unified addressing scheme that automatically handles the multi-memory layout.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10372365B2Virtual addresses for action memories of a hardware forwarding element
Publication Date: 2019.08.06 INTEL CORP
  • US10372365B2 patent drawing
  • US10372365B2 patent drawing
  • US10372365B2 patent drawing

AI summary

Some embodiments provide a method for configuring unit memories of a forwarding element. The method configures a first pool of unit memories to implement several match entries that each include a set of match conditions and an address for an action entry to read when the set of match conditions are met. The method configures a second pool of unit memories to implement several action entries. Each unit memory in the second pool includes a set of action entries that are collectively assigned a virtual memory address. The method moves a particular set of action entries from a first unit memory in the second pool to a second unit memory in the second pool. The particular set of action entries retains a same virtual memory address after moving to the second unit memory.