Virtual Addressing with Lookup Tables for RAID Stripe Storage
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Solution Overview
Problem
As FLASH memory systems increase in density and capacity, the size of the Logical to Physical (L2P) translation table becomes unwieldy, consuming excessive system resources, cost, and power, especially when stored in volatile memory due to access time considerations.
Innovation Solution
Implementing a multistep address translation method that uses virtual addresses to link related address components, reducing table storage requirements and memory access times by employing a RAID system with a processor configured to maintain lookup tables for mapping user logical block addresses to virtual and physical block addresses, and selecting chunks to form pages for data storage across multiple memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a direct L2P translation table is used to map logical addresses to physical addresses in high-density FLASH memory systems, then address translation accuracy is maintained, but the table size becomes unwieldy and consumes excessive system resources, cost, and power
Solution Approach 1:
The patent divides the traditional single L2P translation table into multiple smaller lookup tables organized in a tree structure. Each node in the tree represents a segment of the address space, and leaves represent actual data locations. This segmentation reduces the memory footprint of each individual table while maintaining complete address translation capability through hierarchical navigation.
Solution Approach 2:
The patent introduces a hierarchical dimension to the address translation process by organizing lookup tables in a tree structure with multiple levels. Instead of a flat single-dimensional table, the system uses multi-level hierarchical tables where each level provides partial address translation, reducing the width and depth of individual tables while maintaining comprehensive mapping capability.
2Speed
If a large direct L2P translation table is stored in volatile memory to ensure fast access times, then address translation speed is improved, but physical memory capacity, cost, and power requirements increase
Solution Approach 1:
The patent segments the large translation table into multiple smaller tables that can be distributed across different memory locations or cached more efficiently. This segmentation allows the system to access only the relevant subset of translation entries needed for current operations, reducing the amount of volatile memory that must be continuously powered and maintained at high speed.
Solution Approach 2:
The patent implements preliminary organization of translation data into a hierarchical structure where frequently accessed address ranges can be pre-loaded into smaller, faster memory structures. This preliminary organization enables the system to prepare and cache relevant translation data before it is needed, maintaining fast access times while reducing the overall volatile memory footprint.
3Quantity of substance
If physical memory capacity is reduced to lower cost and power requirements, then system resource efficiency is improved, but address translation capability may be compromised
Solution Approach 1:
The patent uses segmentation to divide the translation functionality across multiple smaller tables, ensuring that no single table becomes a bottleneck or single point of failure. The hierarchical structure provides redundant pathways for address translation, maintaining reliability while using less total memory capacity than a single comprehensive table.
Solution Approach 2:
The patent implements a nested hierarchical structure where smaller lookup tables are nested within a tree framework. Each level of the hierarchy contains references to or actual data from subordinate levels, creating a compact nested structure that maintains complete address translation capability while using less memory than a flat equivalent structure.
Data Source
AI summary
A method of relating the user logical block address (LBA) of a page of user data to the physical block address (PBA) where the data is stored in a RAID architecture reduces to size of the tables by constraining the location to which data of a plurality of LBAs may be written. Chunks of data from a plurality of LBAs may be stored in a common page of memory and the common memory pages is described by a virtual block address (VBA) referencing the PBA, and each of the LBAs uses the same VBA to read the data.