Virtual Architecture Generation for Reconfigurable Processor Binary Optimization
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Solution Overview
Problem
The complexity of generating binary files for reconfigurable processors increases the time required to find an optimal solution, limiting developer intervention and compiler efficiency in determining hardware usage and functionality.
Innovation Solution
A method is introduced to generate virtual architectures corresponding to applications, allowing for the analysis of application requirements and features, and the creation of multiple binary files based on these architectures to optimize execution performance, with the ability to select the best-performing binary file and migrate applications across reconfigurable processors for load balancing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the compiler generates binary files based on full hardware description of reconfigurable processor, then the binary file generation covers all available resources, but the complexity of generating binary file greatly increases and long period of time is required
Solution Approach 1:
The patent segments the binary file generation process by introducing virtual architectures that divide the full hardware description into multiple manageable virtual configurations. Each virtual architecture represents a subset of hardware resources, allowing the compiler to generate multiple simpler binary files corresponding to different virtual architectures rather than one complex binary file covering all hardware.
Solution Approach 2:
The patent adds a virtual architecture dimension between the physical hardware and the application binary. This intermediate layer allows applications to be compiled for virtual architectures rather than directly for the full physical hardware, reducing compilation complexity while maintaining adaptability through runtime virtual architecture selection.
2Extent of automation
If the compiler determines both hardware usage and hardware operation, then complete hardware control is achieved, but developer intervention is reduced and compiler burden increases
Solution Approach 1:
The patent introduces virtual architectures as an intermediary layer between the compiler and physical hardware. This intermediary allows developers to specify hardware usage at a higher level of abstraction without needing to manage the full complexity of hardware operation, while the compiler still achieves complete hardware control through the virtual architecture interface.
3Productivity
If multiple virtual architectures are generated and multiple binary files are created, then execution performance can be optimized by selecting best-performing binary, but the initial generation and selection process becomes more complex
Solution Approach 1:
The patent applies preliminary action by generating multiple binary files for different virtual architectures in advance, before runtime execution. Performance evaluation and selection are performed during binary generation or loading phase, so that at runtime the system can directly load the pre-selected optimal binary file without complex real-time evaluation, reducing runtime complexity while maintaining performance optimization benefits.
Data Source
AI summary
A virtual architecture generating apparatus and method, a runtime system, a multi-core system, and methods of operating the runtime system and the multi-core system may include analyzing a requirement of an application, a feature of the application, and a requirement of a system enabling an execution of the application, and include generating a virtual architecture corresponding to the application, based on a physical architecture of a reconfigurable processor, the analyzed requirements and the analyzed feature.