Virtual Bridge IC Modeling for Consolidated SoC Interconnections
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for designing integrated circuits, such as system-on-chip (SoC), face challenges in efficiently managing complex interconnections and consolidating system-level address maps, leading to increased computational burden and complexity in the design process.
Innovation Solution
A method and system that generate a canonical model from an elaborated integrated circuit model, incorporating a virtual bridge to consolidate all interconnections and memory maps into a simplified data structure, reducing complexity and facilitating efficient design modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an elaborated model with detailed interconnections is used to represent the integrated circuit design, then the design accuracy and completeness are improved, but the computational burden and complexity increase
Solution Approach 1:
The patent segments the complex interconnection model into two parts: a simplified canonical model for computational operations and a detailed elaborated model for design accuracy. The canonical model contains consolidated address maps and interconnections, while the elaborated model preserves full design detail. This segmentation allows the system to work with simplified representations during computation while maintaining access to detailed models when needed.
Solution Approach 2:
The patent creates a canonical model as a simplified copy or abstraction of the elaborated model. The canonical model replicates the essential connectivity and address mapping information in a consolidated format that is computationally efficient, while the original elaborated model remains available for detailed design work. This copying approach allows dual benefits of simplified computation and detailed representation.
2Reliability
If detailed interconnections are maintained in the model, then the design completeness is improved, but the time required for design modifications and exports increases
Solution Approach 1:
The patent performs preliminary consolidation of interconnections into the canonical model before design modifications are needed. By pre-processing the elaborated model into a simplified canonical form with consolidated address maps and interconnections, the system prepares a ready-to-use representation that enables rapid modifications and exports without repeatedly processing the full detailed model.
Solution Approach 2:
The patent separates design representation into a canonical model for rapid modification and export operations, and an elaborated model for detailed design work. This segmentation allows modifications to be performed on the smaller canonical model while the detailed elaborated model remains unchanged, significantly reducing modification time while preserving design completeness.
3Productivity
If a simplified model is used for computational operations, then the processing speed is improved, but the detail and accuracy of design information is reduced
Solution Approach 1:
The patent creates a canonical model as a computational copy that contains consolidated address maps and interconnections sufficient for most processing operations. This copy provides the necessary design information at a reduced complexity level, enabling faster processing while maintaining adequate accuracy for computational tasks. The original detailed model remains available when full design detail is required.
Solution Approach 2:
The patent applies different levels of model detail to different operational contexts. The canonical model with consolidated information is used for computational operations where high processing speed is needed, while the elaborated model with full detail is used for design review and detailed analysis. This local quality approach matches model complexity to operational requirements, optimizing both speed and information retention.
Data Source
AI summary
A computer-aided design method includes accessing an elaborated model of an integrated circuit. The elaborated model includes a first plurality of source buses, a second plurality of addressable components, and a third plurality of interconnections between the source buses and the components. The method further includes generating a canonical model from the elaborated model. The canonical model includes a source bus interface for each one of the source buses and a component interface for each one of the components. The plurality of interconnections between the components and the sources are consolidated. Exports are generated from the canonical model instead of the elaborated model.